upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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95 lines
2.2 KiB
95 lines
2.2 KiB
/*
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* K2L: Clock management APIs
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_CLOCK_K2L_H
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#define __ASM_ARCH_CLOCK_K2L_H
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enum ext_clk_e {
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sys_clk,
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alt_core_clk,
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pa_clk,
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tetris_clk,
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ddr3_clk,
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pcie_clk,
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sgmii_clk,
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usb_clk,
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rp1_clk,
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ext_clk_count /* number of external clocks */
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};
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extern unsigned int external_clk[ext_clk_count];
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#define CLK_LIST(CLK)\
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CLK(0, core_pll_clk)\
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CLK(1, pass_pll_clk)\
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CLK(2, tetris_pll_clk)\
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CLK(3, ddr3_pll_clk)\
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CLK(4, sys_clk0_clk)\
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CLK(5, sys_clk0_1_clk)\
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CLK(6, sys_clk0_2_clk)\
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CLK(7, sys_clk0_3_clk)\
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CLK(8, sys_clk0_4_clk)\
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CLK(9, sys_clk0_6_clk)\
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CLK(10, sys_clk0_8_clk)\
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CLK(11, sys_clk0_12_clk)\
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CLK(12, sys_clk0_24_clk)\
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CLK(13, sys_clk1_clk)\
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CLK(14, sys_clk1_3_clk)\
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CLK(15, sys_clk1_4_clk)\
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CLK(16, sys_clk1_6_clk)\
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CLK(17, sys_clk1_12_clk)\
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CLK(18, sys_clk2_clk)\
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CLK(19, sys_clk3_clk)\
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#define PLLSET_CMD_LIST "<pa|arm|ddr3>"
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#define KS2_CLK1_6 sys_clk0_6_clk
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/* PLL identifiers */
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enum pll_type_e {
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CORE_PLL,
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PASS_PLL,
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TETRIS_PLL,
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DDR3_PLL,
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};
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enum {
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SPD800,
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SPD1000,
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SPD1200,
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SPD1350,
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SPD1400,
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SPD_RSV
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};
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#define CORE_PLL_799 {CORE_PLL, 13, 1, 2}
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#define CORE_PLL_983 {CORE_PLL, 16, 1, 2}
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#define CORE_PLL_1000 {CORE_PLL, 114, 7, 2}
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#define CORE_PLL_1167 {CORE_PLL, 19, 1, 2}
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#define CORE_PLL_1198 {CORE_PLL, 39, 2, 2}
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#define CORE_PLL_1228 {CORE_PLL, 20, 1, 2}
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#define PASS_PLL_1228 {PASS_PLL, 20, 1, 2}
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#define PASS_PLL_983 {PASS_PLL, 16, 1, 2}
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#define PASS_PLL_1050 {PASS_PLL, 205, 12, 2}
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#define TETRIS_PLL_491 {TETRIS_PLL, 8, 1, 2}
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#define TETRIS_PLL_737 {TETRIS_PLL, 12, 1, 2}
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#define TETRIS_PLL_799 {TETRIS_PLL, 13, 1, 2}
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#define TETRIS_PLL_983 {TETRIS_PLL, 16, 1, 2}
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#define TETRIS_PLL_1000 {TETRIS_PLL, 114, 7, 2}
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#define TETRIS_PLL_1167 {TETRIS_PLL, 19, 1, 2}
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#define TETRIS_PLL_1198 {TETRIS_PLL, 39, 2, 2}
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#define TETRIS_PLL_1228 {TETRIS_PLL, 20, 1, 2}
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#define TETRIS_PLL_1352 {TETRIS_PLL, 22, 1, 2}
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#define TETRIS_PLL_1401 {TETRIS_PLL, 114, 5, 2}
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#define DDR3_PLL_200 {DDR3_PLL, 4, 1, 2}
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#define DDR3_PLL_400 {DDR3_PLL, 16, 1, 4}
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#define DDR3_PLL_800 {DDR3_PLL, 16, 1, 2}
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#define DDR3_PLL_333 {DDR3_PLL, 20, 1, 6}
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#endif
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