upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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51 lines
2.2 KiB
51 lines
2.2 KiB
/*
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* Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _LPC32XX_CPU_H
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#define _LPC32XX_CPU_H
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/* LPC32XX Memory map */
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/* AHB physical base addresses */
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#define SLC_NAND_BASE 0x20020000 /* SLC NAND Flash registers base */
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#define SSP0_BASE 0x20084000 /* SSP0 registers base */
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#define SD_CARD_BASE 0x20098000 /* SD card interface registers base */
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#define MLC_NAND_BASE 0x200A8000 /* MLC NAND Flash registers base */
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#define DMA_BASE 0x31000000 /* DMA controller registers base */
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#define USB_BASE 0x31020000 /* USB registers base */
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#define LCD_BASE 0x31040000 /* LCD registers base */
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#define ETHERNET_BASE 0x31060000 /* Ethernet registers base */
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#define EMC_BASE 0x31080000 /* EMC configuration registers base */
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/* FAB peripherals base addresses */
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#define CLK_PM_BASE 0x40004000 /* System control registers base */
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#define HS_UART1_BASE 0x40014000 /* High speed UART 1 registers base */
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#define HS_UART2_BASE 0x40018000 /* High speed UART 2 registers base */
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#define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */
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#define RTC_BASE 0x40024000 /* RTC registers base */
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#define GPIO_BASE 0x40028000 /* GPIO registers base */
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#define WDT_BASE 0x4003C000 /* Watchdog timer registers base */
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#define TIMER0_BASE 0x40044000 /* Timer0 registers base */
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#define TIMER1_BASE 0x4004C000 /* Timer1 registers base */
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#define UART_CTRL_BASE 0x40054000 /* UART control regsisters base */
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/* APB peripherals base addresses */
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#define UART3_BASE 0x40080000 /* UART 3 registers base */
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#define UART4_BASE 0x40088000 /* UART 4 registers base */
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#define UART5_BASE 0x40090000 /* UART 5 registers base */
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#define UART6_BASE 0x40098000 /* UART 6 registers base */
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/* External SDRAM Memory Bank base addresses */
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#define EMC_DYCS0_BASE 0x80000000 /* SDRAM DYCS0 base address */
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#define EMC_DYCS1_BASE 0xA0000000 /* SDRAM DYCS1 base address */
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/* External Static Memory Bank base addresses */
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#define EMC_CS0_BASE 0xE0000000
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#define EMC_CS1_BASE 0xE1000000
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#define EMC_CS2_BASE 0xE2000000
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#define EMC_CS3_BASE 0xE3000000
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#endif /* _LPC32XX_CPU_H */
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