upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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140 lines
5.4 KiB
140 lines
5.4 KiB
/*
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* Sunxi platform Push-Push i2c register definition.
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*
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* (c) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
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* http://linux-sunxi.org
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*
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* (c)Copyright 2006-2013
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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* Berg Xing <bergxing@allwinnertech.com>
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* Tom Cubie <tangliang@allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_P2WI_H
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#define _SUNXI_P2WI_H
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#include <linux/types.h>
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#define P2WI_CTRL_RESET (0x1 << 0)
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#define P2WI_CTRL_IRQ_EN (0x1 << 1)
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#define P2WI_CTRL_TRANS_ABORT (0x1 << 6)
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#define P2WI_CTRL_TRANS_START (0x1 << 7)
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#define __P2WI_CC_CLK(n) (((n) & 0xff) << 0)
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#define P2WI_CC_CLK_MASK __P2WI_CC_CLK_DIV(0xff)
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#define __P2WI_CC_CLK_DIV(n) (((n) >> 1) - 1)
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#define P2WI_CC_CLK_DIV(n) \
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__P2WI_CC_CLK(__P2WI_CC_CLK_DIV(n))
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#define P2WI_CC_SDA_OUT_DELAY(n) (((n) & 0x7) << 8)
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#define P2WI_CC_SDA_OUT_DELAY_MASK P2WI_CC_SDA_OUT_DELAY(0x7)
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#define P2WI_IRQ_TRANS_DONE (0x1 << 0)
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#define P2WI_IRQ_TRANS_ERR (0x1 << 1)
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#define P2WI_IRQ_LOAD_BUSY (0x1 << 2)
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#define P2WI_STAT_TRANS_DONE (0x1 << 0)
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#define P2WI_STAT_TRANS_ERR (0x1 << 1)
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#define P2WI_STAT_LOAD_BUSY (0x1 << 2)
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#define __P2WI_STAT_TRANS_ERR(n) (((n) & 0xff) << 8)
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#define P2WI_STAT_TRANS_ERR_MASK __P2WI_STAT_TRANS_ERR_ID(0xff)
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#define __P2WI_STAT_TRANS_ERR_BYTE_1 0x01
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#define __P2WI_STAT_TRANS_ERR_BYTE_2 0x02
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#define __P2WI_STAT_TRANS_ERR_BYTE_3 0x04
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#define __P2WI_STAT_TRANS_ERR_BYTE_4 0x08
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#define __P2WI_STAT_TRANS_ERR_BYTE_5 0x10
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#define __P2WI_STAT_TRANS_ERR_BYTE_6 0x20
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#define __P2WI_STAT_TRANS_ERR_BYTE_7 0x40
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#define __P2WI_STAT_TRANS_ERR_BYTE_8 0x80
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#define P2WI_STAT_TRANS_ERR_BYTE_1 \
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__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_1)
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#define P2WI_STAT_TRANS_ERR_BYTE_2 \
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__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_2)
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#define P2WI_STAT_TRANS_ERR_BYTE_3 \
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__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_3)
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#define P2WI_STAT_TRANS_ERR_BYTE_4 \
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__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_4)
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#define P2WI_STAT_TRANS_ERR_BYTE_5 \
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__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_5)
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#define P2WI_STAT_TRANS_ERR_BYTE_6 \
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__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_6)
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#define P2WI_STAT_TRANS_ERR_BYTE_7 \
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__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_7)
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#define P2WI_STAT_TRANS_ERR_BYTE_8 \
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__P2WI_STAT_TRANS_ERR(__P2WI_STAT_TRANS_ERR_BYTE_8)
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#define P2WI_DATADDR_BYTE_1(n) (((n) & 0xff) << 0)
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#define P2WI_DATADDR_BYTE_1_MASK P2WI_DATADDR_BYTE_1(0xff)
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#define P2WI_DATADDR_BYTE_2(n) (((n) & 0xff) << 8)
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#define P2WI_DATADDR_BYTE_2_MASK P2WI_DATADDR_BYTE_2(0xff)
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#define P2WI_DATADDR_BYTE_3(n) (((n) & 0xff) << 16)
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#define P2WI_DATADDR_BYTE_3_MASK P2WI_DATADDR_BYTE_3(0xff)
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#define P2WI_DATADDR_BYTE_4(n) (((n) & 0xff) << 24)
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#define P2WI_DATADDR_BYTE_4_MASK P2WI_DATADDR_BYTE_4(0xff)
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#define P2WI_DATADDR_BYTE_5(n) (((n) & 0xff) << 0)
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#define P2WI_DATADDR_BYTE_5_MASK P2WI_DATADDR_BYTE_5(0xff)
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#define P2WI_DATADDR_BYTE_6(n) (((n) & 0xff) << 8)
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#define P2WI_DATADDR_BYTE_6_MASK P2WI_DATADDR_BYTE_6(0xff)
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#define P2WI_DATADDR_BYTE_7(n) (((n) & 0xff) << 16)
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#define P2WI_DATADDR_BYTE_7_MASK P2WI_DATADDR_BYTE_7(0xff)
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#define P2WI_DATADDR_BYTE_8(n) (((n) & 0xff) << 24)
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#define P2WI_DATADDR_BYTE_8_MASK P2WI_DATADDR_BYTE_8(0xff)
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#define __P2WI_DATA_NUM_BYTES(n) (((n) & 0x7) << 0)
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#define P2WI_DATA_NUM_BYTES_MASK __P2WI_DATA_NUM_BYTES(0x7)
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#define P2WI_DATA_NUM_BYTES(n) __P2WI_DATA_NUM_BYTES((n) - 1)
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#define P2WI_DATA_NUM_BYTES_READ (0x1 << 4)
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#define P2WI_DATA_BYTE_1(n) (((n) & 0xff) << 0)
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#define P2WI_DATA_BYTE_1_MASK P2WI_DATA_BYTE_1(0xff)
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#define P2WI_DATA_BYTE_2(n) (((n) & 0xff) << 8)
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#define P2WI_DATA_BYTE_2_MASK P2WI_DATA_BYTE_2(0xff)
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#define P2WI_DATA_BYTE_3(n) (((n) & 0xff) << 16)
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#define P2WI_DATA_BYTE_3_MASK P2WI_DATA_BYTE_3(0xff)
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#define P2WI_DATA_BYTE_4(n) (((n) & 0xff) << 24)
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#define P2WI_DATA_BYTE_4_MASK P2WI_DATA_BYTE_4(0xff)
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#define P2WI_DATA_BYTE_5(n) (((n) & 0xff) << 0)
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#define P2WI_DATA_BYTE_5_MASK P2WI_DATA_BYTE_5(0xff)
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#define P2WI_DATA_BYTE_6(n) (((n) & 0xff) << 8)
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#define P2WI_DATA_BYTE_6_MASK P2WI_DATA_BYTE_6(0xff)
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#define P2WI_DATA_BYTE_7(n) (((n) & 0xff) << 16)
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#define P2WI_DATA_BYTE_7_MASK P2WI_DATA_BYTE_7(0xff)
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#define P2WI_DATA_BYTE_8(n) (((n) & 0xff) << 24)
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#define P2WI_DATA_BYTE_8_MASK P2WI_DATA_BYTE_8(0xff)
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#define P2WI_LINECTRL_SDA_CTRL_EN (0x1 << 0)
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#define P2WI_LINECTRL_SDA_OUT_HIGH (0x1 << 1)
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#define P2WI_LINECTRL_SCL_CTRL_EN (0x1 << 2)
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#define P2WI_LINECTRL_SCL_OUT_HIGH (0x1 << 3)
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#define P2WI_LINECTRL_SDA_STATE_HIGH (0x1 << 4)
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#define P2WI_LINECTRL_SCL_STATE_HIGH (0x1 << 5)
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#define P2WI_PM_DEV_ADDR(n) (((n) & 0xff) << 0)
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#define P2WI_PM_DEV_ADDR_MASK P2WI_PM_DEV_ADDR(0xff)
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#define P2WI_PM_CTRL_ADDR(n) (((n) & 0xff) << 8)
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#define P2WI_PM_CTRL_ADDR_MASK P2WI_PM_CTRL_ADDR(0xff)
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#define P2WI_PM_INIT_DATA(n) (((n) & 0xff) << 16)
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#define P2WI_PM_INIT_DATA_MASK P2WI_PM_INIT_DATA(0xff)
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#define P2WI_PM_INIT_SEND (0x1 << 31)
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struct sunxi_p2wi_reg {
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u32 ctrl; /* 0x00 control */
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u32 cc; /* 0x04 clock control */
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u32 irq; /* 0x08 interrupt */
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u32 status; /* 0x0c status */
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u32 dataddr0; /* 0x10 data address 0 */
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u32 dataddr1; /* 0x14 data address 1 */
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u32 numbytes; /* 0x18 num bytes */
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u32 data0; /* 0x1c data buffer 0 */
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u32 data1; /* 0x20 data buffer 1 */
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u32 linectrl; /* 0x24 line control */
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u32 pm; /* 0x28 power management */
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};
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void p2wi_init(void);
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int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data);
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int p2wi_read(const u8 addr, u8 *data);
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int p2wi_write(const u8 addr, u8 data);
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#endif /* _SUNXI_P2WI_H */
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