upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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325 lines
9.8 KiB
325 lines
9.8 KiB
/*
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* Copyright (c) 2011 The Chromium OS Authors.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/* Tegra clock control functions */
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#ifndef _TEGRA_CLOCK_H_
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#define _TEGRA_CLOCK_H_
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/* Set of oscillator frequencies supported in the internal API. */
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enum clock_osc_freq {
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/* All in MHz, so 13_0 is 13.0MHz */
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CLOCK_OSC_FREQ_13_0,
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CLOCK_OSC_FREQ_19_2,
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CLOCK_OSC_FREQ_12_0,
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CLOCK_OSC_FREQ_26_0,
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CLOCK_OSC_FREQ_COUNT,
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};
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/*
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* Note that no Tegra clock register actually uses all of bits 31:28 as
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* the mux field. Rather, bits 30:28, 29:28, or 28 are used. However, in
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* those cases, nothing is stored in the bits about the mux field, so it's
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* safe to pretend that the mux field extends all the way to the end of the
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* register. As such, the U-Boot clock driver is currently a bit lazy, and
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* doesn't distinguish between 31:28, 30:28, 29:28 and 28; it just lumps
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* them all together and pretends they're all 31:28.
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*/
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enum {
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MASK_BITS_31_30,
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MASK_BITS_31_29,
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MASK_BITS_31_28,
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};
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#include <asm/arch/clock-tables.h>
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/* PLL stabilization delay in usec */
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#define CLOCK_PLL_STABLE_DELAY_US 300
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/* return the current oscillator clock frequency */
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enum clock_osc_freq clock_get_osc_freq(void);
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/**
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* Start PLL using the provided configuration parameters.
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*
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* @param id clock id
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* @param divm input divider
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* @param divn feedback divider
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* @param divp post divider 2^n
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* @param cpcon charge pump setup control
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* @param lfcon loop filter setup control
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*
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* @returns monotonic time in us that the PLL will be stable
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*/
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unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
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u32 divp, u32 cpcon, u32 lfcon);
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/**
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* Set PLL output frequency
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*
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* @param clkid clock id
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* @param pllout pll output id
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* @param rate desired output rate
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*
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* @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
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*/
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int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout,
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unsigned rate);
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/**
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* Read low-level parameters of a PLL.
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*
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* @param id clock id to read (note: USB is not supported)
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* @param divm returns input divider
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* @param divn returns feedback divider
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* @param divp returns post divider 2^n
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* @param cpcon returns charge pump setup control
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* @param lfcon returns loop filter setup control
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*
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* @returns 0 if ok, -1 on error (invalid clock id)
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*/
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int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
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u32 *divp, u32 *cpcon, u32 *lfcon);
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/*
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* Enable a clock
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*
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* @param id clock id
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*/
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void clock_enable(enum periph_id clkid);
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/*
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* Disable a clock
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*
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* @param id clock id
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*/
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void clock_disable(enum periph_id clkid);
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/*
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* Set whether a clock is enabled or disabled.
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*
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* @param id clock id
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* @param enable 1 to enable, 0 to disable
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*/
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void clock_set_enable(enum periph_id clkid, int enable);
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/**
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* Reset a peripheral. This puts it in reset, waits for a delay, then takes
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* it out of reset and waits for th delay again.
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*
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* @param periph_id peripheral to reset
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* @param us_delay time to delay in microseconds
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*/
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void reset_periph(enum periph_id periph_id, int us_delay);
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/**
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* Put a peripheral into or out of reset.
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*
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* @param periph_id peripheral to reset
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* @param enable 1 to put into reset, 0 to take out of reset
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*/
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void reset_set_enable(enum periph_id periph_id, int enable);
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/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
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enum crc_reset_id {
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/* Things we can hold in reset for each CPU */
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crc_rst_cpu = 1,
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crc_rst_de = 1 << 4, /* What is de? */
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crc_rst_watchdog = 1 << 8,
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crc_rst_debug = 1 << 12,
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};
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/**
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* Put parts of the CPU complex into or out of reset.\
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*
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* @param cpu cpu number (0 or 1 on Tegra2, 0-3 on Tegra3)
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* @param which which parts of the complex to affect (OR of crc_reset_id)
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* @param reset 1 to assert reset, 0 to de-assert
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*/
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void reset_cmplx_set_enable(int cpu, int which, int reset);
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/**
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* Set the source for a peripheral clock. This plus the divisor sets the
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* clock rate. You need to look up the datasheet to see the meaning of the
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* source parameter as it changes for each peripheral.
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*
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* Warning: This function is only for use pre-relocation. Please use
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* clock_start_periph_pll() instead.
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*
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* @param periph_id peripheral to adjust
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* @param source source clock (0, 1, 2 or 3)
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*/
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void clock_ll_set_source(enum periph_id periph_id, unsigned source);
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/**
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* Set the source and divisor for a peripheral clock. This sets the
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* clock rate. You need to look up the datasheet to see the meaning of the
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* source parameter as it changes for each peripheral.
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*
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* Warning: This function is only for use pre-relocation. Please use
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* clock_start_periph_pll() instead.
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*
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* @param periph_id peripheral to adjust
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* @param source source clock (0, 1, 2 or 3)
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* @param divisor divisor value to use
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*/
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void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
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unsigned divisor);
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/**
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* Start a peripheral PLL clock at the given rate. This also resets the
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* peripheral.
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*
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* @param periph_id peripheral to start
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* @param parent PLL id of required parent clock
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* @param rate Required clock rate in Hz
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* @return rate selected in Hz, or -1U if something went wrong
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*/
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unsigned clock_start_periph_pll(enum periph_id periph_id,
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enum clock_id parent, unsigned rate);
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/**
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* Returns the rate of a peripheral clock in Hz. Since the caller almost
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* certainly knows the parent clock (having just set it) we require that
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* this be passed in so we don't need to work it out.
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*
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* @param periph_id peripheral to start
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* @param parent PLL id of parent clock (used to calculate rate, you
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* must know this!)
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* @return clock rate of peripheral in Hz
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*/
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unsigned long clock_get_periph_rate(enum periph_id periph_id,
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enum clock_id parent);
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/**
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* Adjust peripheral PLL clock to the given rate. This does not reset the
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* peripheral. If a second stage divisor is not available, pass NULL for
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* extra_div. If it is available, then this parameter will return the
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* divisor selected (which will be a power of 2 from 1 to 256).
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*
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* @param periph_id peripheral to start
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* @param parent PLL id of required parent clock
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* @param rate Required clock rate in Hz
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* @param extra_div value for the second-stage divisor (NULL if one is
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not available)
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* @return rate selected in Hz, or -1U if something went wrong
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*/
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unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
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enum clock_id parent, unsigned rate, int *extra_div);
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/**
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* Returns the clock rate of a specified clock, in Hz.
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*
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* @param parent PLL id of clock to check
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* @return rate of clock in Hz
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*/
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unsigned clock_get_rate(enum clock_id clkid);
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/**
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* Start up a UART using low-level calls
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*
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* Prior to relocation clock_start_periph_pll() cannot be called. This
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* function provides a way to set up a UART using low-level calls which
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* do not require BSS.
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*
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* @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
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*/
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void clock_ll_start_uart(enum periph_id periph_id);
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/**
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* Decode a peripheral ID from a device tree node.
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*
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* This works by looking up the peripheral's 'clocks' node and reading out
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* the second cell, which is the clock number / peripheral ID.
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*
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* @param blob FDT blob to use
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* @param node Node to look at
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* @return peripheral ID, or PERIPH_ID_NONE if none
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*/
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enum periph_id clock_decode_periph_id(const void *blob, int node);
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/**
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* Checks if the oscillator bypass is enabled (XOBP bit)
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*
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* @return 1 if bypass is enabled, 0 if not
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*/
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int clock_get_osc_bypass(void);
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/*
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* Checks that clocks are valid and prints a warning if not
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*
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* @return 0 if ok, -1 on error
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*/
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int clock_verify(void);
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/* Initialize the clocks */
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void clock_init(void);
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/* Initialize the PLLs */
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void clock_early_init(void);
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/* Returns a pointer to the clock source register for a peripheral */
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u32 *get_periph_source_reg(enum periph_id periph_id);
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/**
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* Given a peripheral ID and the required source clock, this returns which
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* value should be programmed into the source mux for that peripheral.
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*
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* There is special code here to handle the one source type with 5 sources.
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*
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* @param periph_id peripheral to start
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* @param source PLL id of required parent clock
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* @param mux_bits Set to number of bits in mux register: 2 or 4
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* @param divider_bits Set to number of divider bits (8 or 16)
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* @return mux value (0-4, or -1 if not found)
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*/
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int get_periph_clock_source(enum periph_id periph_id,
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enum clock_id parent, int *mux_bits, int *divider_bits);
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/*
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* Convert a device tree clock ID to our peripheral ID. They are mostly
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* the same but we are very cautious so we check that a valid clock ID is
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* provided.
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*
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* @param clk_id Clock ID according to tegra30 device tree binding
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* @return peripheral ID, or PERIPH_ID_NONE if the clock ID is invalid
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*/
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enum periph_id clk_id_to_periph_id(int clk_id);
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/**
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* Set the output frequency you want for each PLL clock.
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* PLL output frequencies are programmed by setting their N, M and P values.
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* The governing equations are:
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* VCO = (Fi / m) * n, Fo = VCO / (2^p)
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* where Fo is the output frequency from the PLL.
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* Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
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* 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
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* Please see Tegra TRM section 5.3 to get the detail for PLL Programming
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*
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* @param n PLL feedback divider(DIVN)
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* @param m PLL input divider(DIVN)
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* @param p post divider(DIVP)
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* @param cpcon base PLL charge pump(CPCON)
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* @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
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* be overriden), 1 if PLL is already correct
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*/
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int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon);
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/* return 1 if a peripheral ID is in range */
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#define clock_type_id_isvalid(id) ((id) >= 0 && \
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(id) < CLOCK_TYPE_COUNT)
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/* return 1 if a periphc_internal_id is in range */
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#define periphc_internal_id_isvalid(id) ((id) >= 0 && \
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(id) < PERIPHC_COUNT)
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/* SoC-specific TSC init */
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void arch_timer_init(void);
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void tegra30_set_up_pllp(void);
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#endif /* _TEGRA_CLOCK_H_ */
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