upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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140 lines
2.6 KiB
140 lines
2.6 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
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* (C) Copyright 2013 - 2018 Xilinx, Inc.
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*/
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#include <common.h>
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#include <dm/uclass.h>
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#include <fdtdec.h>
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#include <fpga.h>
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#include <mmc.h>
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#include <watchdog.h>
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#include <wdt.h>
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#include <zynqpl.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
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static struct udevice *watchdog_dev;
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#endif
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F)
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int board_early_init_f(void)
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{
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# if defined(CONFIG_WDT)
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/* bss is not cleared at time when watchdog_reset() is called */
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watchdog_dev = NULL;
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# endif
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return 0;
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}
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#endif
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int board_init(void)
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{
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
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if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev)) {
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debug("Watchdog: Not found by seq!\n");
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if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
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puts("Watchdog: Not found!\n");
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return 0;
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}
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}
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wdt_start(watchdog_dev, 0, 0);
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puts("Watchdog: Started\n");
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# endif
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return 0;
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}
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int board_late_init(void)
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{
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switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
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case ZYNQ_BM_QSPI:
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env_set("modeboot", "qspiboot");
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break;
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case ZYNQ_BM_NAND:
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env_set("modeboot", "nandboot");
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break;
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case ZYNQ_BM_NOR:
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env_set("modeboot", "norboot");
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break;
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case ZYNQ_BM_SD:
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env_set("modeboot", "sdboot");
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break;
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case ZYNQ_BM_JTAG:
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env_set("modeboot", "jtagboot");
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break;
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default:
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env_set("modeboot", "");
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break;
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}
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return 0;
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}
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int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
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{
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#if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
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defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
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if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
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CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
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ethaddr, 6))
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printf("I2C EEPROM MAC address read failed\n");
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#endif
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return 0;
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}
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#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
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int dram_init_banksize(void)
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{
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return fdtdec_setup_memory_banksize();
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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zynq_ddrc_init();
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return 0;
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}
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#else
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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zynq_ddrc_init();
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return 0;
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}
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#endif
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#if defined(CONFIG_WATCHDOG)
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/* Called by macro WATCHDOG_RESET */
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void watchdog_reset(void)
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{
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# if !defined(CONFIG_SPL_BUILD)
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static ulong next_reset;
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ulong now;
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if (!watchdog_dev)
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return;
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now = timer_get_us();
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/* Do not reset the watchdog too often */
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if (now > next_reset) {
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wdt_reset(watchdog_dev);
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next_reset = now + 1000;
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}
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# endif
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}
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#endif
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