upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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137 lines
3.6 KiB
137 lines
3.6 KiB
/*
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* (C) Copyright 2001
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* Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
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*
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* Modified during 2003 by
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* Ken Chou, kchou@ieee.org
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <mpc824x.h>
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#include <pci.h>
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int checkboard (void)
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{
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ulong busfreq = get_bus_freq(0);
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char buf[32];
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printf("Board: A3000 Local Bus at %s MHz\n", strmhz(buf, busfreq));
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return 0;
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}
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long int initdram (int board_type)
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{
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int i, cnt;
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volatile uchar * base= CFG_SDRAM_BASE;
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volatile ulong * addr;
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ulong save[32];
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ulong val, ret = 0;
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for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
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addr = (volatile ulong *)base + cnt;
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save[i++] = *addr;
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*addr = ~cnt;
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}
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addr = (volatile ulong *)base;
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save[i] = *addr;
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*addr = 0;
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if (*addr != 0) {
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*addr = save[i];
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goto Done;
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}
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for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
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addr = (volatile ulong *)base + cnt;
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val = *addr;
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*addr = save[--i];
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if (val != ~cnt) {
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ulong new_bank0_end = cnt * sizeof(long) - 1;
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ulong mear1 = mpc824x_mpc107_getreg(MEAR1);
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ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
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mear1 = (mear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
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emear1 = (emear1 & 0xFFFFFF00) |
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((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
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mpc824x_mpc107_setreg(MEAR1, mear1);
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mpc824x_mpc107_setreg(EMEAR1, emear1);
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ret = cnt * sizeof(long);
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goto Done;
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}
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}
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ret = CFG_MAX_RAM_SIZE;
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Done:
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return ret;
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}
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/*
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* Initialize PCI Devices
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*/
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#ifndef CONFIG_PCI_PNP
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static struct pci_config_table pci_a3000_config_table[] = {
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/* vendor, device, class */
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/* bus, dev, func */
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{ PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID,
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PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, /* dp83815 eth0 divice */
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pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
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PCI_ENET0_MEMADDR,
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PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER }},
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_ANY_ID, 0x14, PCI_ANY_ID, /* PCI slot1 */
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pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
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PCI_ENET1_MEMADDR,
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PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER }},
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_ANY_ID, 0x15, PCI_ANY_ID, /* PCI slot2 */
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pci_cfgfunc_config_device, { PCI_ENET2_IOADDR,
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PCI_ENET2_MEMADDR,
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PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER }},
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{ PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
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PCI_ANY_ID, 0x16, PCI_ANY_ID, /* PCI slot3 */
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pci_cfgfunc_config_device, { PCI_ENET3_IOADDR,
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PCI_ENET3_MEMADDR,
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PCI_COMMAND_IO |
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PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER }},
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{ }
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};
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#endif
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struct pci_controller hose = {
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#ifndef CONFIG_PCI_PNP
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config_table: pci_a3000_config_table,
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#endif
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};
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void pci_init_board(void)
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{
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pci_mpc824x_init(&hose);
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}
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