upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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44 lines
1.1 KiB
44 lines
1.1 KiB
/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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* York Sun <yorksun@freescale.com>
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*
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* FSL DIU Framebuffer driver
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include <fsl_diu_fb.h>
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DECLARE_GLOBAL_DATA_PTR;
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void diu_set_pixel_clock(unsigned int pixclock)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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volatile clk512x_t *clk = &immap->clk;
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volatile unsigned int *clkdvdr = &clk->scfr[0];
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unsigned long speed_ccb, temp, pixval;
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speed_ccb = get_bus_freq(0) * 4;
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temp = 1000000000/pixclock;
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temp *= 1000;
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pixval = speed_ccb / temp;
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debug("DIU pixval = %lu\n", pixval);
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/* Modify PXCLK in GUTS CLKDVDR */
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debug("DIU: Current value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr));
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temp = in_be32(clkdvdr) & 0xFFFFFF00;
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out_be32(clkdvdr, temp | (pixval & 0xFF));
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debug("DIU: Modified value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr));
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}
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int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
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{
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unsigned int pixel_format = 0x88883316;
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debug("mpc5121_diu_init\n");
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return fsl_diu_init(xres, yres, pixel_format, 0);
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}
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