upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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52 lines
1.2 KiB
52 lines
1.2 KiB
/*
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* (C) Copyright 2003
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* Martin Winistoerfer, martinwinistoerfer@gmx.ch.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* File: speed.c
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*
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* Discription: Provides cpu speed calculation
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*
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*/
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#include <common.h>
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#include <mpc5xx.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Get cpu and bus clock
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*/
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int get_clocks (void)
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{
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volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
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#ifndef CONFIG_5xx_GCLK_FREQ
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uint divf = (immr->im_clkrst.car_plprcr & PLPRCR_DIVF_MSK);
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uint mf = ((immr->im_clkrst.car_plprcr & PLPRCR_MF_MSK) >> PLPRCR_MF_SHIFT);
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ulong vcoout;
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vcoout = (CONFIG_SYS_OSC_CLK / (divf + 1)) * (mf + 1) * 2;
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if(immr->im_clkrst.car_plprcr & PLPRCR_CSRC_MSK) {
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gd->cpu_clk = vcoout / (2^(((immr->im_clkrst.car_sccr & SCCR_DFNL_MSK) >> SCCR_DFNL_SHIFT) + 1));
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} else {
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gd->cpu_clk = vcoout / (2^(immr->im_clkrst.car_sccr & SCCR_DFNH_MSK));
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}
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#else /* CONFIG_5xx_GCLK_FREQ */
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gd->bus_clk = CONFIG_5xx_GCLK_FREQ;
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#endif /* CONFIG_5xx_GCLK_FREQ */
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if ((immr->im_clkrst.car_sccr & SCCR_EBDF11) == 0) {
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/* No Bus Divider active */
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gd->bus_clk = gd->cpu_clk;
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} else {
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/* CLKOUT is GCLK / 2 */
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gd->bus_clk = gd->cpu_clk / 2;
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}
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return (0);
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}
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