upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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353 lines
12 KiB
353 lines
12 KiB
/*
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* Copyright 2012 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/fsl_serdes.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include "fsl_corenet2_serdes.h"
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struct serdes_config {
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u32 protocol;
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u8 lanes[SRDS_MAX_LANES];
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};
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#ifdef CONFIG_PPC_T4240
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static const struct serdes_config serdes1_cfg_tbl[] = {
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/* SerDes 1 */
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{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10}},
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{2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
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HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
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{4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
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HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
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{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
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{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
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{38, {NONE, NONE, QSGMII_FM1_B, NONE,
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NONE, NONE, QSGMII_FM1_A, NONE}},
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{40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
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NONE, NONE, QSGMII_FM1_A, NONE}},
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{46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
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NONE, NONE, QSGMII_FM1_A, NONE}},
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{48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
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NONE, NONE, QSGMII_FM1_A, NONE}},
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{}
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};
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static const struct serdes_config serdes2_cfg_tbl[] = {
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/* SerDes 2 */
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{1, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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XAUI_FM2_MAC10, XAUI_FM2_MAC10,
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XAUI_FM2_MAC10, XAUI_FM2_MAC10}},
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{2, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
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HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
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{4, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
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HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
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{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{14, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{23, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{38, {NONE, NONE, QSGMII_FM2_B, NONE,
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NONE, NONE, QSGMII_FM2_A, NONE} },
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{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
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NONE, NONE, QSGMII_FM2_A, NONE} },
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{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
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NONE, NONE, QSGMII_FM2_A, NONE} },
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{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
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NONE, NONE, QSGMII_FM2_A, NONE} },
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{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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NONE, NONE, QSGMII_FM2_A, NONE} },
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{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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NONE, NONE, QSGMII_FM2_A, NONE} },
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{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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NONE, NONE, QSGMII_FM2_A, NONE} },
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{56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
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XFI_FM2_MAC10, XFI_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{57, {XFI_FM1_MAC9, XFI_FM1_MAC10,
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XFI_FM2_MAC10, XFI_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
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{}
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};
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static const struct serdes_config serdes3_cfg_tbl[] = {
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/* SerDes 3 */
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{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
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{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
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{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
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{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
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{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
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{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
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{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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PCIE2, PCIE2, PCIE2, PCIE2}},
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{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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PCIE2, PCIE2, PCIE2, PCIE2}},
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{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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SRIO1, SRIO1, SRIO1, SRIO1}},
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{}
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};
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static const struct serdes_config serdes4_cfg_tbl[] = {
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/* SerDes 4 */
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{2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
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{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
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{6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
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{8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
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{10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
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{12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
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{14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
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{16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
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{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
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{}
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};
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#elif defined(CONFIG_PPC_T4160)
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static const struct serdes_config serdes1_cfg_tbl[] = {
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/* SerDes 1 */
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{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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XAUI_FM1_MAC9, XAUI_FM1_MAC9,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10,
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XAUI_FM1_MAC10, XAUI_FM1_MAC10} },
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{2, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
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HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
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{4, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
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HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
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HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
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{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
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{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
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SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
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SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
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SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
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{38, {NONE, NONE, QSGMII_FM1_B, NONE,
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NONE, NONE, QSGMII_FM1_A, NONE} },
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{}
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};
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static const struct serdes_config serdes2_cfg_tbl[] = {
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/* SerDes 2 */
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{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
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{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
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{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
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{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
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{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
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{26, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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NONE, NONE} },
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{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
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{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
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{38, {NONE, NONE, QSGMII_FM2_B, NONE,
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NONE, QSGMII_FM1_A, NONE, NONE} },
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{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
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NONE, QSGMII_FM1_A, NONE, NONE} },
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{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
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NONE, QSGMII_FM1_A, NONE, NONE} },
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{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
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SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
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NONE, QSGMII_FM1_A, NONE, NONE} },
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{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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XAUI_FM2_MAC9, XAUI_FM2_MAC9,
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NONE, NONE, NONE, NONE} },
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{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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NONE, NONE, NONE, NONE} },
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{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
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NONE, NONE, NONE, NONE} },
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{56, {NONE, XFI_FM1_MAC10,
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XFI_FM2_MAC10, NONE,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
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{57, {NONE, XFI_FM1_MAC10,
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XFI_FM2_MAC10, NONE,
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SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
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NONE, NONE} },
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{}
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};
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static const struct serdes_config serdes3_cfg_tbl[] = {
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/* SerDes 3 */
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{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
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{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
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{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
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{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
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{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
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{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
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{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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PCIE2, PCIE2, PCIE2, PCIE2} },
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{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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PCIE2, PCIE2, PCIE2, PCIE2} },
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{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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SRIO1, SRIO1, SRIO1, SRIO1} },
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{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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SRIO1, SRIO1, SRIO1, SRIO1} },
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{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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SRIO1, SRIO1, SRIO1, SRIO1} },
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{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
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NONE, NONE, NONE, NONE} },
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{}
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};
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static const struct serdes_config serdes4_cfg_tbl[] = {
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/* SerDes 4 */
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{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
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{6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
|
|
{8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
|
|
{10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
|
|
{12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
|
|
{14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
|
|
{16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
|
|
{18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
|
|
{}
|
|
}
|
|
;
|
|
#else
|
|
#error "Need to define SerDes protocol"
|
|
#endif
|
|
static const struct serdes_config *serdes_cfg_tbl[] = {
|
|
serdes1_cfg_tbl,
|
|
serdes2_cfg_tbl,
|
|
serdes3_cfg_tbl,
|
|
serdes4_cfg_tbl,
|
|
};
|
|
|
|
enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
|
|
{
|
|
const struct serdes_config *ptr;
|
|
|
|
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
|
|
return 0;
|
|
|
|
ptr = serdes_cfg_tbl[serdes];
|
|
while (ptr->protocol) {
|
|
if (ptr->protocol == cfg)
|
|
return ptr->lanes[lane];
|
|
ptr++;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
int is_serdes_prtcl_valid(int serdes, u32 prtcl)
|
|
{
|
|
int i;
|
|
const struct serdes_config *ptr;
|
|
|
|
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
|
|
return 0;
|
|
|
|
ptr = serdes_cfg_tbl[serdes];
|
|
while (ptr->protocol) {
|
|
if (ptr->protocol == prtcl)
|
|
break;
|
|
ptr++;
|
|
}
|
|
|
|
if (!ptr->protocol)
|
|
return 0;
|
|
|
|
for (i = 0; i < SRDS_MAX_LANES; i++) {
|
|
if (ptr->lanes[i] != NONE)
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|