upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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508 lines
15 KiB
508 lines
15 KiB
/*
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* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Andreas Heppel <aheppel@sysgo.de>
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*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* PCI routines
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*/
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#include <common.h>
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#include <bootretry.h>
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#include <cli.h>
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#include <command.h>
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#include <console.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <pci.h>
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/*
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* Follows routines for the output of infos about devices on PCI bus.
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*/
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void pci_header_show(pci_dev_t dev);
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void pci_header_show_brief(pci_dev_t dev);
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/*
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* Subroutine: pciinfo
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*
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* Description: Show information about devices on PCI bus.
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* Depending on the define CONFIG_SYS_SHORT_PCI_LISTING
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* the output will be more or less exhaustive.
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*
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* Inputs: bus_no the number of the bus to be scanned.
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*
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* Return: None
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*
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*/
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void pciinfo(int BusNum, int ShortPCIListing)
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{
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struct pci_controller *hose = pci_bus_to_hose(BusNum);
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int Device;
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int Function;
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unsigned char HeaderType;
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unsigned short VendorID;
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pci_dev_t dev;
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int ret;
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if (!hose)
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return;
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printf("Scanning PCI devices on bus %d\n", BusNum);
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if (ShortPCIListing) {
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printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
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printf("_____________________________________________________________\n");
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}
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for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
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HeaderType = 0;
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VendorID = 0;
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for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
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/*
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* If this is not a multi-function device, we skip the rest.
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*/
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if (Function && !(HeaderType & 0x80))
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break;
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dev = PCI_BDF(BusNum, Device, Function);
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if (pci_skip_dev(hose, dev))
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continue;
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ret = pci_read_config_word(dev, PCI_VENDOR_ID,
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&VendorID);
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if (ret)
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goto error;
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if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
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continue;
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if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
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if (ShortPCIListing)
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{
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printf("%02x.%02x.%02x ", BusNum, Device, Function);
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pci_header_show_brief(dev);
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}
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else
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{
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printf("\nFound PCI device %02x.%02x.%02x:\n",
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BusNum, Device, Function);
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pci_header_show(dev);
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}
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}
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}
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return;
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error:
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printf("Cannot read bus configuration: %d\n", ret);
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}
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/*
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* Subroutine: pci_header_show_brief
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*
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* Description: Reads and prints the header of the
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* specified PCI device in short form.
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*
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* Inputs: dev Bus+Device+Function number
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*
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* Return: None
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*
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*/
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void pci_header_show_brief(pci_dev_t dev)
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{
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u16 vendor, device;
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u8 class, subclass;
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pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
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pci_read_config_word(dev, PCI_DEVICE_ID, &device);
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pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
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pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
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printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
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vendor, device,
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pci_class_str(class), subclass);
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}
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/*
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* Subroutine: PCI_Header_Show
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*
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* Description: Reads the header of the specified PCI device.
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*
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* Inputs: BusDevFunc Bus+Device+Function number
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*
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* Return: None
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*
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*/
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void pci_header_show(pci_dev_t dev)
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{
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u8 _byte, header_type;
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u16 _word;
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u32 _dword;
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#define PRINT(msg, type, reg) \
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pci_read_config_##type(dev, reg, &_##type); \
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printf(msg, _##type)
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#define PRINT2(msg, type, reg, func) \
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pci_read_config_##type(dev, reg, &_##type); \
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printf(msg, _##type, func(_##type))
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pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
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PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
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PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
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PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
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PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
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PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
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PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
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pci_class_str);
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PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
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PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
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PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
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PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
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PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
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PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
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PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
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switch (header_type & 0x03) {
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case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
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PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
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PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
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PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
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PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
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PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
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PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
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PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
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PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
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PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
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PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
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PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
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PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
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PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
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break;
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case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
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PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
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PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
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PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
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PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
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PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
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PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
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PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
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PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
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PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
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PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
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PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
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PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
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PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
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PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
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PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
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PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
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PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
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PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
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PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
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PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
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break;
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case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
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PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
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PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
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PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
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PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
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PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
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PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
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PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
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PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
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PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
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PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
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PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
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PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
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PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
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PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
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PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
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PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
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PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
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PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
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PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
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PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
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PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
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PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
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PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
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PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
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break;
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default:
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printf("unknown header\n");
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break;
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}
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#undef PRINT
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#undef PRINT2
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}
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/* Convert the "bus.device.function" identifier into a number.
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*/
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static pci_dev_t get_pci_dev(char* name)
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{
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char cnum[12];
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int len, i, iold, n;
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int bdfs[3] = {0,0,0};
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len = strlen(name);
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if (len > 8)
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return -1;
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for (i = 0, iold = 0, n = 0; i < len; i++) {
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if (name[i] == '.') {
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memcpy(cnum, &name[iold], i - iold);
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cnum[i - iold] = '\0';
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bdfs[n++] = simple_strtoul(cnum, NULL, 16);
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iold = i + 1;
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}
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}
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strcpy(cnum, &name[iold]);
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if (n == 0)
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n = 1;
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bdfs[n] = simple_strtoul(cnum, NULL, 16);
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return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
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}
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static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
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{
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#define DISP_LINE_LEN 16
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ulong i, nbytes, linebytes;
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int rc = 0;
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if (length == 0)
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length = 0x40 / size; /* Standard PCI configuration space */
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/* Print the lines.
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* once, and all accesses are with the specified bus width.
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*/
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nbytes = length * size;
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do {
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uint val4;
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ushort val2;
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u_char val1;
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printf("%08lx:", addr);
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linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
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for (i=0; i<linebytes; i+= size) {
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if (size == 4) {
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pci_read_config_dword(bdf, addr, &val4);
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printf(" %08x", val4);
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} else if (size == 2) {
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pci_read_config_word(bdf, addr, &val2);
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printf(" %04x", val2);
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} else {
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pci_read_config_byte(bdf, addr, &val1);
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printf(" %02x", val1);
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}
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addr += size;
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}
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printf("\n");
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nbytes -= linebytes;
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if (ctrlc()) {
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rc = 1;
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break;
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}
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} while (nbytes > 0);
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return (rc);
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}
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static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
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{
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if (size == 4) {
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pci_write_config_dword(bdf, addr, value);
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}
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else if (size == 2) {
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ushort val = value & 0xffff;
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pci_write_config_word(bdf, addr, val);
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}
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else {
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u_char val = value & 0xff;
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pci_write_config_byte(bdf, addr, val);
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}
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return 0;
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}
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static int
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pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
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{
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ulong i;
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int nbytes;
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uint val4;
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ushort val2;
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u_char val1;
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/* Print the address, followed by value. Then accept input for
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* the next value. A non-converted value exits.
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*/
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do {
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printf("%08lx:", addr);
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if (size == 4) {
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pci_read_config_dword(bdf, addr, &val4);
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printf(" %08x", val4);
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}
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else if (size == 2) {
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pci_read_config_word(bdf, addr, &val2);
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printf(" %04x", val2);
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}
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else {
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pci_read_config_byte(bdf, addr, &val1);
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printf(" %02x", val1);
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}
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nbytes = cli_readline(" ? ");
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if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
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/* <CR> pressed as only input, don't modify current
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* location and move to next. "-" pressed will go back.
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*/
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if (incrflag)
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addr += nbytes ? -size : size;
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nbytes = 1;
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/* good enough to not time out */
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bootretry_reset_cmd_timeout();
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}
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#ifdef CONFIG_BOOT_RETRY_TIME
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else if (nbytes == -2) {
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break; /* timed out, exit the command */
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}
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#endif
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else {
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char *endp;
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i = simple_strtoul(console_buffer, &endp, 16);
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nbytes = endp - console_buffer;
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if (nbytes) {
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/* good enough to not time out
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*/
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bootretry_reset_cmd_timeout();
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pci_cfg_write (bdf, addr, size, i);
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if (incrflag)
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addr += size;
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}
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}
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} while (nbytes);
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return 0;
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}
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/* PCI Configuration Space access commands
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*
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* Syntax:
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* pci display[.b, .w, .l] bus.device.function} [addr] [len]
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* pci next[.b, .w, .l] bus.device.function [addr]
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* pci modify[.b, .w, .l] bus.device.function [addr]
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* pci write[.b, .w, .l] bus.device.function addr value
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*/
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static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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ulong addr = 0, value = 0, size = 0;
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pci_dev_t bdf = 0;
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char cmd = 's';
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if (argc > 1)
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cmd = argv[1][0];
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switch (cmd) {
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case 'd': /* display */
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case 'n': /* next */
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case 'm': /* modify */
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case 'w': /* write */
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/* Check for a size specification. */
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size = cmd_get_data_size(argv[1], 4);
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if (argc > 3)
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addr = simple_strtoul(argv[3], NULL, 16);
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if (argc > 4)
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value = simple_strtoul(argv[4], NULL, 16);
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case 'h': /* header */
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if (argc < 3)
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goto usage;
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if ((bdf = get_pci_dev(argv[2])) == -1)
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return 1;
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break;
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#ifdef CONFIG_CMD_PCI_ENUM
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case 'e':
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break;
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#endif
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default: /* scan bus */
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value = 1; /* short listing */
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bdf = 0; /* bus number */
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if (argc > 1) {
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if (argv[argc-1][0] == 'l') {
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value = 0;
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argc--;
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}
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if (argc > 1)
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bdf = simple_strtoul(argv[1], NULL, 16);
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}
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pciinfo(bdf, value);
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return 0;
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}
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switch (argv[1][0]) {
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case 'h': /* header */
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pci_header_show(bdf);
|
|
return 0;
|
|
case 'd': /* display */
|
|
return pci_cfg_display(bdf, addr, size, value);
|
|
#ifdef CONFIG_CMD_PCI_ENUM
|
|
case 'e':
|
|
pci_init();
|
|
return 0;
|
|
#endif
|
|
case 'n': /* next */
|
|
if (argc < 4)
|
|
goto usage;
|
|
return pci_cfg_modify(bdf, addr, size, value, 0);
|
|
case 'm': /* modify */
|
|
if (argc < 4)
|
|
goto usage;
|
|
return pci_cfg_modify(bdf, addr, size, value, 1);
|
|
case 'w': /* write */
|
|
if (argc < 5)
|
|
goto usage;
|
|
return pci_cfg_write(bdf, addr, size, value);
|
|
}
|
|
|
|
return 1;
|
|
usage:
|
|
return CMD_RET_USAGE;
|
|
}
|
|
|
|
/***************************************************/
|
|
|
|
#ifdef CONFIG_SYS_LONGHELP
|
|
static char pci_help_text[] =
|
|
"[bus] [long]\n"
|
|
" - short or long list of PCI devices on bus 'bus'\n"
|
|
#ifdef CONFIG_CMD_PCI_ENUM
|
|
"pci enum\n"
|
|
" - re-enumerate PCI buses\n"
|
|
#endif
|
|
"pci header b.d.f\n"
|
|
" - show header of PCI device 'bus.device.function'\n"
|
|
"pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
|
|
" - display PCI configuration space (CFG)\n"
|
|
"pci next[.b, .w, .l] b.d.f address\n"
|
|
" - modify, read and keep CFG address\n"
|
|
"pci modify[.b, .w, .l] b.d.f address\n"
|
|
" - modify, auto increment CFG address\n"
|
|
"pci write[.b, .w, .l] b.d.f address value\n"
|
|
" - write to CFG address";
|
|
#endif
|
|
|
|
U_BOOT_CMD(
|
|
pci, 5, 1, do_pci,
|
|
"list and access PCI Configuration Space", pci_help_text
|
|
);
|
|
|