upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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82 lines
2.4 KiB
82 lines
2.4 KiB
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2011 Andes Technology Corporation
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*/
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#ifndef __AG102_H
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#define __AG102_H
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/*
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* Hardware register bases
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*/
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/* PCI Controller */
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#define CONFIG_FTPCI100_BASE 0x90000000
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/* LPC Controller */
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#define CONFIG_LPC_IO_BASE 0x90100000
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/* LPC Controller */
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#define CONFIG_LPC_BASE 0x90200000
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/* NDS32 Data Local Memory 01 */
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#define CONFIG_NDS_DLM1_BASE 0x90300000
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/* NDS32 Data Local Memory 02 */
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#define CONFIG_NDS_DLM2_BASE 0x90400000
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/* Synopsys DWC DDR2/1 Controller */
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#define CONFIG_DWCDDR21MCTL_BASE 0x90500000
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/* DMA Controller */
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#define CONFIG_FTDMAC020_BASE 0x90600000
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/* FTIDE020_S IDE (ATA) Controller */
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#define CONFIG_FTIDE020S_BASE 0x90700000
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/* USB OTG Controller */
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#define CONFIG_FZOTG266HD0A_BASE 0x90800000
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/* Andes L2 Cache Controller */
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#define CONFIG_NCEL2C100_BASE 0x90900000
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/* XGI XG22 GPU */
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#define CONFIG_XGI_XG22_BASE 0x90A00000
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/* GMAC Ethernet Controller */
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#define CONFIG_FTGMAC100_BASE 0x90B00000
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/* AHB Controller */
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#define CONFIG_FTAHBC020S_BASE 0x90C00000
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/* AHB-to-APB Bridge Controller */
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#define CONFIG_FTAPBBRG020S_01_BASE 0x90D00000
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/* External AHB2AHB Controller */
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#define CONFIG_EXT_AHB2AHB_BASE 0x90E00000
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/* Andes Multi-core Interrupt Controller */
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#define CONFIG_NCEMIC100_BASE 0x90F00000
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/*
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* APB Device definitions
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*/
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/* Compat Flash Controller */
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#define CONFIG_FTCFC010_BASE 0x94000000
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/* APB - SSP (SPI) (without AC97) Controller */
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#define CONFIG_FTSSP010_01_BASE 0x94100000
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/* UART1 - APB STUART Controller (UART0 in Linux) */
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#define CONFIG_FTUART010_01_BASE 0x94200000
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/* APB - SSP with HDA/AC97 Controller */
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#define CONFIG_FTSSP010_02_BASE 0x94500000
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/* UART2 - APB STUART Controller (UART1 in Linux) */
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#define CONFIG_FTUART010_02_BASE 0x94600000
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/* PCU Controller */
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#define CONFIG_ANDES_PCU_BASE 0x94800000
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/* FTTMR010 Timer */
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#define CONFIG_FTTMR010_BASE 0x94900000
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/* Watch Dog Controller */
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#define CONFIG_FTWDT010_BASE 0x94A00000
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/* FTRTC010 Real Time Clock */
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#define CONFIG_FTRTC010_BASE 0x98B00000
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/* GPIO Controller */
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#define CONFIG_FTGPIO010_BASE 0x94C00000
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/* I2C Controller */
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#define CONFIG_FTIIC010_BASE 0x94E00000
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/* PWM - Pulse Width Modulator Controller */
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#define CONFIG_FTPWM010_BASE 0x94F00000
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/* Debug LED */
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#define CONFIG_DEBUG_LED 0x902FFFFC
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/* Power Management Unit */
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#define CONFIG_FTPMU010_BASE 0x98100000
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#endif /* __AG102_H */
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