upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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148 lines
3.0 KiB
148 lines
3.0 KiB
/* SPARC stack layout Macros and structures,
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* mainly taken from BCC (the Bare C compiler for
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* SPARC LEON2/3) sources.
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*
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* (C) Copyright 2007
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* Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __SPARC_STACK_H__
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#define __SPARC_STACK_H__
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#include <asm/ptrace.h>
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#ifndef __ASSEMBLER__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define PT_REGS_SZ sizeof(struct pt_regs)
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/* A Sparc stack frame */
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struct sparc_stackframe_regs {
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unsigned long sf_locals[8];
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unsigned long sf_ins[6];
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struct sparc_stackframe_regs *sf_fp;
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unsigned long sf_callers_pc;
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char *sf_structptr;
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unsigned long sf_xargs[6];
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unsigned long sf_xxargs[1];
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};
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#define SF_REGS_SZ sizeof(struct sparc_stackframe_regs)
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/* A register window */
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struct sparc_regwindow_regs {
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unsigned long locals[8];
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unsigned long ins[8];
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};
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#define RW_REGS_SZ sizeof(struct sparc_regwindow_regs)
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/* A fpu window */
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struct sparc_fpuwindow_regs {
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unsigned long locals[32];
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unsigned long fsr;
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unsigned long lastctx;
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};
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#define FW_REGS_SZ sizeof(struct sparc_fpuwindow_regs)
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#ifdef __cplusplus
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}
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#endif
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#else
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#define PT_REGS_SZ 0x50 /* 20*4 */
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#define SF_REGS_SZ 0x60 /* 24*4 */
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#define RW_REGS_SZ 0x20 /* 16*4 */
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#define FW_REGS_SZ 0x88 /* 34*4 */
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#endif /* !ASM */
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/* These are for pt_regs. */
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#define PT_PSR 0x0
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#define PT_PC 0x4
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#define PT_NPC 0x8
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#define PT_Y 0xc
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#define PT_G0 0x10
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#define PT_WIM PT_G0
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#define PT_G1 0x14
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#define PT_G2 0x18
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#define PT_G3 0x1c
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#define PT_G4 0x20
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#define PT_G5 0x24
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#define PT_G6 0x28
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#define PT_G7 0x2c
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#define PT_I0 0x30
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#define PT_I1 0x34
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#define PT_I2 0x38
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#define PT_I3 0x3c
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#define PT_I4 0x40
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#define PT_I5 0x44
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#define PT_I6 0x48
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#define PT_FP PT_I6
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#define PT_I7 0x4c
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/* Stack_frame offsets */
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#define SF_L0 0x00
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#define SF_L1 0x04
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#define SF_L2 0x08
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#define SF_L3 0x0c
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#define SF_L4 0x10
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#define SF_L5 0x14
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#define SF_L6 0x18
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#define SF_L7 0x1c
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#define SF_I0 0x20
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#define SF_I1 0x24
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#define SF_I2 0x28
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#define SF_I3 0x2c
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#define SF_I4 0x30
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#define SF_I5 0x34
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#define SF_FP 0x38
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#define SF_PC 0x3c
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#define SF_RETP 0x40
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#define SF_XARG0 0x44
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#define SF_XARG1 0x48
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#define SF_XARG2 0x4c
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#define SF_XARG3 0x50
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#define SF_XARG4 0x54
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#define SF_XARG5 0x58
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#define SF_XXARG 0x5c
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/* Reg_window offsets */
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#define RW_L0 0x00
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#define RW_L1 0x04
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#define RW_L2 0x08
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#define RW_L3 0x0c
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#define RW_L4 0x10
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#define RW_L5 0x14
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#define RW_L6 0x18
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#define RW_L7 0x1c
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#define RW_I0 0x20
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#define RW_I1 0x24
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#define RW_I2 0x28
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#define RW_I3 0x2c
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#define RW_I4 0x30
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#define RW_I5 0x34
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#define RW_I6 0x38
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#define RW_I7 0x3c
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/* Fpu_window offsets */
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#define FW_F0 0x00
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#define FW_F2 0x08
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#define FW_F4 0x10
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#define FW_F6 0x18
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#define FW_F8 0x20
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#define FW_F10 0x28
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#define FW_F12 0x30
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#define FW_F14 0x38
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#define FW_F16 0x40
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#define FW_F18 0x48
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#define FW_F20 0x50
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#define FW_F22 0x58
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#define FW_F24 0x60
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#define FW_F26 0x68
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#define FW_F28 0x70
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#define FW_F30 0x78
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#define FW_FSR 0x80
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#endif
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