upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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367 lines
10 KiB
367 lines
10 KiB
/*
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* MPC8260 SCC Ethernet
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*
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* Copyright (c) 2000 MontaVista Software, Inc. Dan Malek (dmalek@jlc.net)
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*
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* (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright (c) 2001
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* Advent Networks, Inc. <http://www.adventnetworks.com>
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* Jay Monkman <jtm@smoothsmoothie.com>
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*
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* Modified so that it plays nicely when more than one ETHERNET interface
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* is in use a la ether_fcc.c.
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* (C) Copyright 2008
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* DENX Software Engineerin GmbH
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* Gary Jennejohn <garyj@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/cpm_8260.h>
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#include <mpc8260.h>
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#include <malloc.h>
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#include <net.h>
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#include <command.h>
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#include <config.h>
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#if (CONFIG_ETHER_INDEX == 1)
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# define PROFF_ENET PROFF_SCC1
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# define CPM_CR_ENET_PAGE CPM_CR_SCC1_PAGE
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# define CPM_CR_ENET_SBLOCK CPM_CR_SCC1_SBLOCK
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# define CMXSCR_MASK (CMXSCR_SC1 |\
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CMXSCR_RS1CS_MSK |\
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CMXSCR_TS1CS_MSK)
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#elif (CONFIG_ETHER_INDEX == 2)
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# define PROFF_ENET PROFF_SCC2
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# define CPM_CR_ENET_PAGE CPM_CR_SCC2_PAGE
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# define CPM_CR_ENET_SBLOCK CPM_CR_SCC2_SBLOCK
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# define CMXSCR_MASK (CMXSCR_SC2 |\
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CMXSCR_RS2CS_MSK |\
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CMXSCR_TS2CS_MSK)
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#elif (CONFIG_ETHER_INDEX == 3)
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# define PROFF_ENET PROFF_SCC3
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# define CPM_CR_ENET_PAGE CPM_CR_SCC3_PAGE
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# define CPM_CR_ENET_SBLOCK CPM_CR_SCC3_SBLOCK
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# define CMXSCR_MASK (CMXSCR_SC3 |\
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CMXSCR_RS3CS_MSK |\
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CMXSCR_TS3CS_MSK)
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#elif (CONFIG_ETHER_INDEX == 4)
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# define PROFF_ENET PROFF_SCC4
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# define CPM_CR_ENET_PAGE CPM_CR_SCC4_PAGE
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# define CPM_CR_ENET_SBLOCK CPM_CR_SCC4_SBLOCK
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# define CMXSCR_MASK (CMXSCR_SC4 |\
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CMXSCR_RS4CS_MSK |\
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CMXSCR_TS4CS_MSK)
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#endif
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/* Ethernet Transmit and Receive Buffers */
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#define DBUF_LENGTH 1520
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#define TX_BUF_CNT 2
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#if !defined(CONFIG_SYS_SCC_TOUT_LOOP)
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#define CONFIG_SYS_SCC_TOUT_LOOP 1000000
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#endif
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static char txbuf[TX_BUF_CNT][ DBUF_LENGTH ];
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static uint rxIdx; /* index of the current RX buffer */
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static uint txIdx; /* index of the current TX buffer */
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/*
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* SCC Ethernet Tx and Rx buffer descriptors allocated at the
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* immr->udata_bd address on Dual-Port RAM
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* Provide for Double Buffering
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*/
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typedef volatile struct CommonBufferDescriptor {
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cbd_t rxbd[PKTBUFSRX]; /* Rx BD */
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cbd_t txbd[TX_BUF_CNT]; /* Tx BD */
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} RTXBD;
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static RTXBD *rtx;
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static int sec_send(struct eth_device *dev, void *packet, int length)
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{
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int i;
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int result = 0;
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if (length <= 0) {
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printf("scc: bad packet size: %d\n", length);
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goto out;
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}
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for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
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if (i >= CONFIG_SYS_SCC_TOUT_LOOP) {
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puts ("scc: tx buffer not ready\n");
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goto out;
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}
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}
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rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
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rtx->txbd[txIdx].cbd_datlen = length;
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rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |
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BD_ENET_TX_WRAP);
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for(i=0; rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY; i++) {
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if (i >= CONFIG_SYS_SCC_TOUT_LOOP) {
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puts ("scc: tx error\n");
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goto out;
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}
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}
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/* return only status bits */
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result = rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS;
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out:
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return result;
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}
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static int sec_rx(struct eth_device *dev)
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{
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int length;
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for (;;)
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{
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if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
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length = -1;
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break; /* nothing received - leave for() loop */
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}
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length = rtx->rxbd[rxIdx].cbd_datlen;
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if (rtx->rxbd[rxIdx].cbd_sc & 0x003f)
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{
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printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
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}
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else
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{
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/* Pass the packet up to the protocol layers. */
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net_process_received_packet(net_rx_packets[rxIdx], length - 4);
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}
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/* Give the buffer back to the SCC. */
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rtx->rxbd[rxIdx].cbd_datlen = 0;
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/* wrap around buffer index when necessary */
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if ((rxIdx + 1) >= PKTBUFSRX) {
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rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP |
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BD_ENET_RX_EMPTY);
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rxIdx = 0;
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}
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else {
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rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
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rxIdx++;
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}
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}
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return length;
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}
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/**************************************************************
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*
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* SCC Ethernet Initialization Routine
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*
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*************************************************************/
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static int sec_init(struct eth_device *dev, bd_t *bis)
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{
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int i;
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volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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scc_enet_t *pram_ptr;
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uint dpaddr;
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uchar ea[6];
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rxIdx = 0;
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txIdx = 0;
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/*
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* Assign static pointer to BD area.
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* Avoid exhausting DPRAM, which would cause a panic.
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*/
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if (rtx == NULL) {
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dpaddr = m8260_cpm_dpalloc(sizeof(RTXBD) + 2, 16);
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rtx = (RTXBD *)&immr->im_dprambase[dpaddr];
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}
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/* 24.21 - (1-3): ioports have been set up already */
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/* 24.21 - (4,5): connect SCC's tx and rx clocks, use NMSI for SCC */
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immr->im_cpmux.cmx_uar = 0;
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immr->im_cpmux.cmx_scr = ( (immr->im_cpmux.cmx_scr & ~CMXSCR_MASK) |
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CONFIG_SYS_CMXSCR_VALUE);
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/* 24.21 (6) write RBASE and TBASE to parameter RAM */
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pram_ptr = (scc_enet_t *)&(immr->im_dprambase[PROFF_ENET]);
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pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]);
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pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]);
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pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Nrml Ops and Mot byte ordering */
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pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Nrml access */
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pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. package len 1520 */
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pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */
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pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */
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/* 24.21 - (7): Write INIT RX AND TX PARAMETERS to CPCR */
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while(immr->im_cpm.cp_cpcr & CPM_CR_FLG);
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immr->im_cpm.cp_cpcr = mk_cr_cmd(CPM_CR_ENET_PAGE,
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CPM_CR_ENET_SBLOCK,
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0x0c,
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CPM_CR_INIT_TRX) | CPM_CR_FLG;
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/* 24.21 - (8-18): Set up parameter RAM */
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pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */
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pram_ptr->sen_alec = 0x0; /* Align Error Counter (unused) */
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pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */
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pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */
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pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */
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pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */
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pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */
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pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */
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pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */
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pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */
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pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */
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pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */
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pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */
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eth_getenv_enetaddr("ethaddr", ea);
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pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
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pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
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pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
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pram_ptr->sen_pper = 0x0; /* Persistence (unused) */
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pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */
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pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */
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pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */
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pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */
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pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */
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pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */
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pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */
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/* 24.21 - (19): Initialize RxBD */
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for (i = 0; i < PKTBUFSRX; i++)
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{
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rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
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rtx->rxbd[i].cbd_datlen = 0; /* Reset */
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rtx->rxbd[i].cbd_bufaddr = (uint)net_rx_packets[i];
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}
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rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
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/* 24.21 - (20): Initialize TxBD */
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for (i = 0; i < TX_BUF_CNT; i++)
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{
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rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD |
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BD_ENET_TX_LAST |
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BD_ENET_TX_TC);
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rtx->txbd[i].cbd_datlen = 0; /* Reset */
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rtx->txbd[i].cbd_bufaddr = (uint)&txbuf[i][0];
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}
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rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
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/* 24.21 - (21): Write 0xffff to SCCE */
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immr->im_scc[CONFIG_ETHER_INDEX-1].scc_scce = ~(0x0);
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/* 24.21 - (22): Write to SCCM to enable TXE, RXF, TXB events */
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immr->im_scc[CONFIG_ETHER_INDEX-1].scc_sccm = (SCCE_ENET_TXE |
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SCCE_ENET_RXF |
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SCCE_ENET_TXB);
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/* 24.21 - (23): we don't use ethernet interrupts */
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/* 24.21 - (24): Clear GSMR_H to enable normal operations */
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immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrh = 0;
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/* 24.21 - (25): Clear GSMR_L to enable normal operations */
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immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl = (SCC_GSMRL_TCI |
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SCC_GSMRL_TPL_48 |
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SCC_GSMRL_TPP_10 |
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SCC_GSMRL_MODE_ENET);
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/* 24.21 - (26): Initialize DSR */
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immr->im_scc[CONFIG_ETHER_INDEX-1].scc_dsr = 0xd555;
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/* 24.21 - (27): Initialize PSMR2
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*
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* Settings:
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* CRC = 32-Bit CCITT
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* NIB = Begin searching for SFD 22 bits after RENA
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* FDE = Full Duplex Enable
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* BRO = Reject broadcast packets
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* PROMISCOUS = Catch all packets regardless of dest. MAC adress
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*/
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immr->im_scc[CONFIG_ETHER_INDEX-1].scc_psmr = SCC_PSMR_ENCRC |
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SCC_PSMR_NIB22 |
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#if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
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SCC_PSMR_FDE |
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#endif
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#if defined(CONFIG_SCC_ENET_NO_BROADCAST)
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SCC_PSMR_BRO |
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#endif
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#if defined(CONFIG_SCC_ENET_PROMISCOUS)
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SCC_PSMR_PRO |
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#endif
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0;
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/* 24.21 - (28): Write to GSMR_L to enable SCC */
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immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
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SCC_GSMRL_ENT);
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return 0;
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}
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static void sec_halt(struct eth_device *dev)
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{
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volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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immr->im_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl &= ~(SCC_GSMRL_ENR |
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SCC_GSMRL_ENT);
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}
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#if 0
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static void sec_restart(void)
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{
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volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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immr->im_cpm.cp_scc[CONFIG_ETHER_INDEX-1].scc_gsmrl |= (SCC_GSMRL_ENR |
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SCC_GSMRL_ENT);
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}
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#endif
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int mpc82xx_scc_enet_initialize(bd_t *bis)
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{
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struct eth_device *dev;
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dev = (struct eth_device *) malloc(sizeof *dev);
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memset(dev, 0, sizeof *dev);
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sprintf(dev->name, "SCC");
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dev->init = sec_init;
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dev->halt = sec_halt;
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dev->send = sec_send;
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dev->recv = sec_rx;
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eth_register(dev);
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return 1;
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}
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