upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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144 lines
2.6 KiB
144 lines
2.6 KiB
/*
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* Copyright (c) 2016 Google, Inc
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*
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* Modified from coreboot
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/intel_regs.h>
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#include <asm/io.h>
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#include <asm/arch/pch.h>
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#define IOBP_RETRY 1000
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/* IO Buffer Programming */
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#define IOBPIRI 0x2330
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#define IOBPD 0x2334
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#define IOBPS 0x2338
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#define IOBPS_READY 0x0001
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#define IOBPS_TX_MASK 0x0006
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#define IOBPS_MASK 0xff00
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#define IOBPS_READ 0x0600
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#define IOBPS_WRITE 0x0700
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#define IOBPU 0x233a
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#define IOBPU_MAGIC 0xf000
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#define IOBP_PCICFG_READ 0x0400
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#define IOBP_PCICFG_WRITE 0x0500
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static inline int iobp_poll(void)
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{
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unsigned try;
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for (try = IOBP_RETRY; try > 0; try--) {
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u16 status = readw(RCB_REG(IOBPS));
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if ((status & IOBPS_READY) == 0)
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return 1;
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udelay(10);
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}
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printf("IOBP: timeout waiting for transaction to complete\n");
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return 0;
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}
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int pch_iobp_trans_start(u32 address, int op)
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{
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if (!iobp_poll())
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return 0;
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/* Set the address */
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writel(address, RCB_REG(IOBPIRI));
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/* READ OPCODE */
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clrsetbits_le16(RCB_REG(IOBPS), IOBPS_MASK, op);
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return 1;
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}
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int pch_iobp_trans_finish(void)
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{
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u16 status;
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/* Undocumented magic */
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writew(IOBPU_MAGIC, RCB_REG(IOBPU));
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/* Set ready bit */
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setbits_le16(RCB_REG(IOBPS), IOBPS_READY);
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if (!iobp_poll())
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return 1;
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/* Check for successful transaction */
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status = readw(RCB_REG(IOBPS));
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if (status & IOBPS_TX_MASK)
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return 1;
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return 0;
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}
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u32 pch_iobp_read(u32 address)
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{
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if (!pch_iobp_trans_start(address, IOBPS_READ))
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return 0;
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if (pch_iobp_trans_finish()) {
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printf("IOBP: read 0x%08x failed\n", address);
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return 0;
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}
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/* Read IOBP data */
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return readl(RCB_REG(IOBPD));
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}
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int pch_iobp_write(u32 address, u32 data)
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{
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if (!pch_iobp_trans_start(address, IOBPS_WRITE))
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return -EIO;
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writel(data, RCB_REG(IOBPD));
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if (pch_iobp_trans_finish()) {
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printf("IOBP: write 0x%08x failed\n", address);
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return -EIO;
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}
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return 0;
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}
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int pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
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{
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u32 data = pch_iobp_read(address);
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/* Update the data */
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data &= andvalue;
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data |= orvalue;
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return pch_iobp_write(address, data);
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}
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int pch_iobp_exec(u32 addr, u16 op_code, u8 route_id, u32 *data, u8 *resp)
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{
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if (!data || !resp)
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return 0;
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*resp = -1;
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if (!iobp_poll())
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return -EIO;
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writel(addr, RCB_REG(IOBPIRI));
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clrsetbits_le16(RCB_REG(IOBPS), 0xff00, op_code);
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writew(IOBPU_MAGIC | route_id, RCB_REG(IOBPU));
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writel(*data, RCB_REG(IOBPD));
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/* Set IOBPS[0] to trigger IOBP transaction*/
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setbits_le16(RCB_REG(IOBPS), 1);
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if (!iobp_poll())
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return -EIO;
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*resp = (readw(RCB_REG(IOBPS)) & IOBPS_TX_MASK) >> 1;
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*data = readl(RCB_REG(IOBPD));
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return 0;
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}
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