upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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123 lines
3.4 KiB
123 lines
3.4 KiB
/*
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* (C) Copyright 2000-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/immap.h>
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int checkboard (void) {
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puts ("Board: Freescale M5271EVB\n");
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return 0;
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};
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phys_size_t initdram (int board_type) {
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int i;
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/* Enable Address lines 23-21 and lower 16bits of data path */
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mbar_writeByte(MCF_GPIO_PAR_AD, MCF_GPIO_AD_ADDR23 |
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MCF_GPIO_AD_ADDR22 | MCF_GPIO_AD_ADDR21 |
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MCF_GPIO_AD_DATAL);
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/* Set CS2 pin to be SD_CS0 */
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mbar_writeByte(MCF_GPIO_PAR_CS, mbar_readByte(MCF_GPIO_PAR_CS)
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| MCF_GPIO_PAR_CS_PAR_CS2);
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/* Configure SDRAM Control Pin Assignemnt Register */
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mbar_writeByte(MCF_GPIO_PAR_SDRAM, MCF_GPIO_SDRAM_CSSDCS_00 |
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MCF_GPIO_SDRAM_SDWE | MCF_GPIO_SDRAM_SCAS |
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MCF_GPIO_SDRAM_SRAS | MCF_GPIO_SDRAM_SCKE |
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MCF_GPIO_SDRAM_SDCS_11);
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/*
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* Check to see if the SDRAM has already been initialized
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* by a run control tool
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*/
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if (!(mbar_readLong(MCF_SDRAMC_DACR0) & MCF_SDRAMC_DACRn_RE)) {
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/* Initialize DRAM Control Register: DCR */
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mbar_writeShort(MCF_SDRAMC_DCR,
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MCF_SDRAMC_DCR_RTIM(0x01)
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| MCF_SDRAMC_DCR_RC(0x30));
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/*
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* Initialize DACR0
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*
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* CASL: 01
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* CBM: cmd at A20, bank select bits 21 and up
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* PS: 32bit port size
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*/
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mbar_writeLong(MCF_SDRAMC_DACR0,
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MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18)
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| MCF_SDRAMC_DACRn_CASL(1)
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| MCF_SDRAMC_DACRn_CBM(3)
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| MCF_SDRAMC_DACRn_PS(0));
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/* Initialize DMR0 */
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mbar_writeLong(MCF_SDRAMC_DMR0,
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MCF_SDRAMC_DMRn_BAM_16M
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| MCF_SDRAMC_DMRn_V);
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/* Set IP bit in DACR */
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mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
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| MCF_SDRAMC_DACRn_IP);
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/* Wait at least 20ns to allow banks to precharge */
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for (i = 0; i < 5; i++)
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asm(" nop");
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/* Write to this block to initiate precharge */
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*(u32 *)(CFG_SDRAM_BASE) = 0xa5a5a5a5;
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/* Set RE bit in DACR */
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mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
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| MCF_SDRAMC_DACRn_RE);
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/* Wait for at least 8 auto refresh cycles to occur */
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for (i = 0; i < 2000; i++)
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asm(" nop");
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/* Finish the configuration by issuing the MRS */
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mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
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| MCF_SDRAMC_DACRn_MRS);
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/*
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* Write to the SDRAM Mode Register A0-A11 = 0x400
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*
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* Write Burst Mode = Programmed Burst Length
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* Op Mode = Standard Op
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* CAS Latency = 2
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* Burst Type = Sequential
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* Burst Length = 1
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*/
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*(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
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}
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return CFG_SDRAM_SIZE * 1024 * 1024;
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};
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int testdram (void) {
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/* TODO: XXX XXX XXX */
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printf ("DRAM test not implemented!\n");
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return (0);
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}
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