upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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254 lines
6.6 KiB
254 lines
6.6 KiB
/*
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* VR4131 PCIU support code for TANBAC Evaluation board TB0229.
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*
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* (C) Masami Komiya <mkomiya@sonare.it> 2004
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2, or (at
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* your option) any later version.
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/addrspace.h>
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#define VR4131_PCIMMAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c00)
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#define VR4131_PCIMMAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c04)
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#define VR4131_PCITAW1REG (volatile unsigned int *)(CKSEG1 + 0x0f000c08)
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#define VR4131_PCITAW2REG (volatile unsigned int *)(CKSEG1 + 0x0f000c0c)
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#define VR4131_PCIMIOAWREG (volatile unsigned int *)(CKSEG1 + 0x0f000c10)
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#define VR4131_PCICONFDREG (volatile unsigned int *)(CKSEG1 + 0x0f000c14)
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#define VR4131_PCICONFAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c18)
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#define VR4131_PCIMAILREG (volatile unsigned int *)(CKSEG1 + 0x0f000c1c)
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#define VR4131_BUSERRADREG (volatile unsigned int *)(CKSEG1 + 0x0f000c24)
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#define VR4131_INTCNTSTAREG (volatile unsigned int *)(CKSEG1 + 0x0f000c28)
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#define VR4131_PCIEXACCREG (volatile unsigned int *)(CKSEG1 + 0x0f000c2c)
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#define VR4131_PCIRECONTREG (volatile unsigned int *)(CKSEG1 + 0x0f000c30)
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#define VR4131_PCIENREG (volatile unsigned int *)(CKSEG1 + 0x0f000c34)
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#define VR4131_PCICLKSELREG (volatile unsigned int *)(CKSEG1 + 0x0f000c38)
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#define VR4131_PCITRDYREG (volatile unsigned int *)(CKSEG1 + 0x0f000c3c)
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#define VR4131_PCICLKRUNREG (volatile unsigned int *)(CKSEG1 + 0x0f000c60)
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#define VR4131_PCIHOSTCONFIG (volatile unsigned int *)(CKSEG1 + 0x0f000d00)
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#define VR4131_VENDORIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00)
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#define VR4131_DEVICEIDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d00)
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#define VR4131_COMMANDREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04)
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#define VR4131_STATUSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d04)
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#define VR4131_REVREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08)
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#define VR4131_CLASSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d08)
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#define VR4131_CACHELSREG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c)
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#define VR4131_LATTIMERRG (volatile unsigned int *)(CKSEG1 + 0x0f000d0c)
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#define VR4131_MAILBAREG (volatile unsigned int *)(CKSEG1 + 0x0f000d10)
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#define VR4131_PCIMBA1REG (volatile unsigned int *)(CKSEG1 + 0x0f000d14)
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#define VR4131_PCIMBA2REG (volatile unsigned int *)(CKSEG1 + 0x0f000d18)
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/*#define VR41XX_PCIIRQ_OFFSET (VR41XX_IRQ_MAX + 1) */
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/*#define VR41XX_PCIIRQ_MAX (VR41XX_IRQ_MAX + 12) */
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/*#define VR4122_PCI_HOST_BASE 0xa0000000 */
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volatile unsigned int *pciconfigaddr;
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volatile unsigned int *pciconfigdata;
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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/*
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* Access PCI Configuration Register for VR4131
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*/
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static int vr4131_pci_config_access (u8 access_type, u32 dev, u32 reg,
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u32 * data)
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{
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u32 bus;
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u32 device;
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bus = ((dev & 0xff0000) >> 16);
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device = ((dev & 0xf800) >> 11);
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if (bus == 0) {
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/* Type 0 Configuration */
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*VR4131_PCICONFAREG = (u32) (1UL << device | (reg & 0xfc));
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} else {
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/* Type 1 Configuration */
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*VR4131_PCICONFAREG = (u32) (dev | ((reg / 4) << 2) | 1);
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}
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if (access_type == PCI_ACCESS_WRITE) {
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*VR4131_PCICONFDREG = *data;
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} else {
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*data = *VR4131_PCICONFDREG;
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}
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return (0);
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}
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static int vr4131_pci_read_config_byte (u32 hose, u32 dev, u32 reg, u8 * val)
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{
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u32 data;
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if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
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return -1;
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*val = (data >> ((reg & 3) << 3)) & 0xff;
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return 0;
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}
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static int vr4131_pci_read_config_word (u32 hose, u32 dev, u32 reg, u16 * val)
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{
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u32 data;
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if (reg & 1)
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return -1;
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if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
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return -1;
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*val = (data >> ((reg & 3) << 3)) & 0xffff;
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return 0;
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}
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static int vr4131_pci_read_config_dword (u32 hose, u32 dev, u32 reg,
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u32 * val)
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{
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u32 data = 0;
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if (reg & 3)
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return -1;
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if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
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return -1;
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*val = data;
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return (0);
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}
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static int vr4131_pci_write_config_byte (u32 hose, u32 dev, u32 reg, u8 val)
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{
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u32 data = 0;
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if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
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return -1;
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data = (data & ~(0xff << ((reg & 3) << 3))) | (val <<
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((reg & 3) << 3));
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if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
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return -1;
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return 0;
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}
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static int vr4131_pci_write_config_word (u32 hose, u32 dev, u32 reg, u16 val)
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{
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u32 data = 0;
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if (reg & 1)
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return -1;
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if (vr4131_pci_config_access (PCI_ACCESS_READ, dev, reg, &data))
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return -1;
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data = (data & ~(0xffff << ((reg & 3) << 3))) | (val <<
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((reg & 3) << 3));
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if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
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return -1;
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return 0;
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}
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static int vr4131_pci_write_config_dword (u32 hose, u32 dev, u32 reg, u32 val)
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{
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u32 data;
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if (reg & 3) {
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return -1;
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}
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data = val;
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if (vr4131_pci_config_access (PCI_ACCESS_WRITE, dev, reg, &data))
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return -1;
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return (0);
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}
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/*
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* Initialize VR4131 PCIU
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*/
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vr4131_pciu_init ()
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{
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/* PCI clock */
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*VR4131_PCICLKSELREG = 0x00000002;
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/* PCI memory and I/O space */
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*VR4131_PCIMMAW1REG = 0x100F9010;
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*VR4131_PCIMMAW2REG = 0x140FD014;
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*VR4131_PCIMIOAWREG = 0x160FD000;
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/* Target memory window */
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*VR4131_PCITAW1REG = 0x00081000; /* 64MB */
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*VR4131_PCITAW2REG = 0x00000000;
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*VR4131_MAILBAREG = 0UL;
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*VR4131_PCIMBA1REG = 0UL;
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*VR4131_PCITRDYREG = 0x00008004;
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*VR4131_PCIENREG = 0x00000004; /* PCI enable */
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*VR4131_COMMANDREG = 0x02000007;
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}
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/*
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* Initialize Module
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*/
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void init_vr4131_pci (struct pci_controller *hose)
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{
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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vr4131_pciu_init (); /* Initialize VR4131 PCIU */
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/* PCI memory space #1 */
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pci_set_region (hose->regions + 0,
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0x10000000, 0xb0000000, 0x04000000, PCI_REGION_MEM);
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/* PCI memory space #2 */
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pci_set_region (hose->regions + 1,
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0x14000000, 0xb4000000, 0x02000000, PCI_REGION_MEM);
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/* PCI I/O space */
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pci_set_region (hose->regions + 2,
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0x16000000, 0xb6000000, 0x02000000, PCI_REGION_IO);
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/* System memory space */
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pci_set_region (hose->regions + 3,
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0x00000000,
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0x80000000,
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0x04000000, PCI_REGION_MEM | PCI_REGION_MEMORY);
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hose->region_count = 4;
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hose->read_byte = vr4131_pci_read_config_byte;
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hose->read_word = vr4131_pci_read_config_word;
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hose->read_dword = vr4131_pci_read_config_dword;
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hose->write_byte = vr4131_pci_write_config_byte;
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hose->write_word = vr4131_pci_write_config_word;
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hose->write_dword = vr4131_pci_write_config_dword;
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pci_register_hose (hose);
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hose->last_busno = pci_hose_scan (hose);
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return;
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}
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