upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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354 lines
9.9 KiB
354 lines
9.9 KiB
/*
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* fec.h -- Fast Ethernet Controller definitions
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*
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* Some definitions copied from commproc.h for MPC8xx:
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* MPC8xx Communication Processor Module.
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* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
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*
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* Add FEC Structure and definitions
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef fec_h
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#define fec_h
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/* Buffer descriptors used FEC.
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*/
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typedef struct cpm_buf_desc {
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ushort cbd_sc; /* Status and Control */
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ushort cbd_datlen; /* Data length in buffer */
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uint cbd_bufaddr; /* Buffer address in host memory */
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} cbd_t;
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#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */
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#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
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#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
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#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
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#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
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#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
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#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
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#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
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#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
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#define BD_SC_BR ((ushort)0x0020) /* Break received */
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#define BD_SC_FR ((ushort)0x0010) /* Framing error */
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#define BD_SC_PR ((ushort)0x0008) /* Parity error */
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#define BD_SC_OV ((ushort)0x0002) /* Overrun */
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#define BD_SC_CD ((ushort)0x0001) /* Carrier Detect lost */
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/* Buffer descriptor control/status used by Ethernet receive.
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*/
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#define BD_ENET_RX_EMPTY ((ushort)0x8000)
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#define BD_ENET_RX_RO1 ((ushort)0x4000)
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#define BD_ENET_RX_WRAP ((ushort)0x2000)
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#define BD_ENET_RX_INTR ((ushort)0x1000)
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#define BD_ENET_RX_RO2 BD_ENET_RX_INTR
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#define BD_ENET_RX_LAST ((ushort)0x0800)
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#define BD_ENET_RX_FIRST ((ushort)0x0400)
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#define BD_ENET_RX_MISS ((ushort)0x0100)
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#define BD_ENET_RX_BC ((ushort)0x0080)
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#define BD_ENET_RX_MC ((ushort)0x0040)
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#define BD_ENET_RX_LG ((ushort)0x0020)
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#define BD_ENET_RX_NO ((ushort)0x0010)
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#define BD_ENET_RX_SH ((ushort)0x0008)
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#define BD_ENET_RX_CR ((ushort)0x0004)
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#define BD_ENET_RX_OV ((ushort)0x0002)
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#define BD_ENET_RX_CL ((ushort)0x0001)
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#define BD_ENET_RX_TR BD_ENET_RX_CL
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#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
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/* Buffer descriptor control/status used by Ethernet transmit.
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*/
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#define BD_ENET_TX_READY ((ushort)0x8000)
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#define BD_ENET_TX_PAD ((ushort)0x4000)
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#define BD_ENET_TX_TO1 BD_ENET_TX_PAD
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#define BD_ENET_TX_WRAP ((ushort)0x2000)
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#define BD_ENET_TX_INTR ((ushort)0x1000)
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#define BD_ENET_TX_TO2 BD_ENET_TX_INTR_
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#define BD_ENET_TX_LAST ((ushort)0x0800)
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#define BD_ENET_TX_TC ((ushort)0x0400)
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#define BD_ENET_TX_DEF ((ushort)0x0200)
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#define BD_ENET_TX_ABC BD_ENET_TX_DEF
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#define BD_ENET_TX_HB ((ushort)0x0100)
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#define BD_ENET_TX_LC ((ushort)0x0080)
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#define BD_ENET_TX_RL ((ushort)0x0040)
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#define BD_ENET_TX_RCMASK ((ushort)0x003c)
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#define BD_ENET_TX_UN ((ushort)0x0002)
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#define BD_ENET_TX_CSL ((ushort)0x0001)
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#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
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/*********************************************************************
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* Fast Ethernet Controller (FEC)
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*********************************************************************/
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/* FEC private information */
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struct fec_info_s {
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int index;
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u32 iobase;
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u32 pinmux;
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u32 miibase;
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int phy_addr;
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int dup_spd;
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char *phy_name;
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int phyname_init;
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cbd_t *rxbd; /* Rx BD */
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cbd_t *txbd; /* Tx BD */
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uint rxIdx;
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uint txIdx;
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char *txbuf;
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int initialized;
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struct fec_info_s *next;
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};
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#ifdef CONFIG_MCFFEC
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/* Register read/write struct */
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typedef struct fec {
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#ifdef CONFIG_M5272
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u32 ecr; /* 0x00 */
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u32 eir; /* 0x04 */
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u32 eimr; /* 0x08 */
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u32 ivsr; /* 0x0C */
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u32 rdar; /* 0x10 */
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u32 tdar; /* 0x14 */
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u8 resv1[0x28]; /* 0x18 */
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u32 mmfr; /* 0x40 */
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u32 mscr; /* 0x44 */
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u8 resv2[0x44]; /* 0x48 */
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u32 frbr; /* 0x8C */
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u32 frsr; /* 0x90 */
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u8 resv3[0x10]; /* 0x94 */
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u32 tfwr; /* 0xA4 */
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u32 res4; /* 0xA8 */
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u32 tfsr; /* 0xAC */
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u8 resv4[0x50]; /* 0xB0 */
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u32 opd; /* 0x100 - dummy */
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u32 rcr; /* 0x104 */
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u32 mibc; /* 0x108 */
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u8 resv5[0x38]; /* 0x10C */
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u32 tcr; /* 0x144 */
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u8 resv6[0x270]; /* 0x148 */
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u32 iaur; /* 0x3B8 - dummy */
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u32 ialr; /* 0x3BC - dummy */
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u32 palr; /* 0x3C0 */
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u32 paur; /* 0x3C4 */
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u32 gaur; /* 0x3C8 */
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u32 galr; /* 0x3CC */
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u32 erdsr; /* 0x3D0 */
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u32 etdsr; /* 0x3D4 */
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u32 emrbr; /* 0x3D8 */
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u8 resv12[0x74]; /* 0x18C */
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#else
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u8 resv0[0x4];
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u32 eir;
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u32 eimr;
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u8 resv1[0x4];
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u32 rdar;
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u32 tdar;
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u8 resv2[0xC];
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u32 ecr;
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u8 resv3[0x18];
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u32 mmfr;
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u32 mscr;
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u8 resv4[0x1C];
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u32 mibc;
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u8 resv5[0x1C];
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u32 rcr;
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u8 resv6[0x3C];
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u32 tcr;
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u8 resv7[0x1C];
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u32 palr;
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u32 paur;
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u32 opd;
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u8 resv8[0x28];
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u32 iaur;
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u32 ialr;
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u32 gaur;
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u32 galr;
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u8 resv9[0x1C];
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u32 tfwr;
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u8 resv10[0x4];
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u32 frbr;
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u32 frsr;
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u8 resv11[0x2C];
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u32 erdsr;
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u32 etdsr;
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u32 emrbr;
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u8 resv12[0x74];
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#endif
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u32 rmon_t_drop;
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u32 rmon_t_packets;
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u32 rmon_t_bc_pkt;
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u32 rmon_t_mc_pkt;
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u32 rmon_t_crc_align;
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u32 rmon_t_undersize;
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u32 rmon_t_oversize;
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u32 rmon_t_frag;
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u32 rmon_t_jab;
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u32 rmon_t_col;
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u32 rmon_t_p64;
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u32 rmon_t_p65to127;
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u32 rmon_t_p128to255;
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u32 rmon_t_p256to511;
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u32 rmon_t_p512to1023;
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u32 rmon_t_p1024to2047;
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u32 rmon_t_p_gte2048;
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u32 rmon_t_octets;
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u32 ieee_t_drop;
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u32 ieee_t_frame_ok;
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u32 ieee_t_1col;
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u32 ieee_t_mcol;
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u32 ieee_t_def;
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u32 ieee_t_lcol;
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u32 ieee_t_excol;
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u32 ieee_t_macerr;
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u32 ieee_t_cserr;
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u32 ieee_t_sqe;
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u32 ieee_t_fdxfc;
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u32 ieee_t_octets_ok;
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u8 resv13[0x8];
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u32 rmon_r_drop;
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u32 rmon_r_packets;
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u32 rmon_r_bc_pkt;
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u32 rmon_r_mc_pkt;
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u32 rmon_r_crc_align;
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u32 rmon_r_undersize;
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u32 rmon_r_oversize;
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u32 rmon_r_frag;
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u32 rmon_r_jab;
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u32 rmon_r_resvd_0;
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u32 rmon_r_p64;
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u32 rmon_r_p65to127;
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u32 rmon_r_p128to255;
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u32 rmon_r_p256to511;
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u32 rmon_r_p512to1023;
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u32 rmon_r_p1024to2047;
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u32 rmon_r_p_gte2048;
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u32 rmon_r_octets;
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u32 ieee_r_drop;
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u32 ieee_r_frame_ok;
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u32 ieee_r_crc;
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u32 ieee_r_align;
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u32 ieee_r_macerr;
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u32 ieee_r_fdxfc;
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u32 ieee_r_octets_ok;
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} fec_t;
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#endif /* CONFIG_MCFFEC */
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/*********************************************************************
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* Fast Ethernet Controller (FEC)
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*********************************************************************/
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/* Bit definitions and macros for FEC_EIR */
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#define FEC_EIR_CLEAR_ALL (0xFFF80000)
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#define FEC_EIR_HBERR (0x80000000)
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#define FEC_EIR_BABR (0x40000000)
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#define FEC_EIR_BABT (0x20000000)
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#define FEC_EIR_GRA (0x10000000)
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#define FEC_EIR_TXF (0x08000000)
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#define FEC_EIR_TXB (0x04000000)
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#define FEC_EIR_RXF (0x02000000)
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#define FEC_EIR_RXB (0x01000000)
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#define FEC_EIR_MII (0x00800000)
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#define FEC_EIR_EBERR (0x00400000)
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#define FEC_EIR_LC (0x00200000)
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#define FEC_EIR_RL (0x00100000)
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#define FEC_EIR_UN (0x00080000)
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/* Bit definitions and macros for FEC_RDAR */
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#define FEC_RDAR_R_DES_ACTIVE (0x01000000)
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/* Bit definitions and macros for FEC_TDAR */
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#define FEC_TDAR_X_DES_ACTIVE (0x01000000)
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/* Bit definitions and macros for FEC_ECR */
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#define FEC_ECR_ETHER_EN (0x00000002)
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#define FEC_ECR_RESET (0x00000001)
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/* Bit definitions and macros for FEC_MMFR */
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#define FEC_MMFR_DATA(x) (((x)&0xFFFF))
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#define FEC_MMFR_ST(x) (((x)&0x03)<<30)
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#define FEC_MMFR_ST_01 (0x40000000)
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#define FEC_MMFR_OP_RD (0x20000000)
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#define FEC_MMFR_OP_WR (0x10000000)
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#define FEC_MMFR_PA(x) (((x)&0x1F)<<23)
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#define FEC_MMFR_RA(x) (((x)&0x1F)<<18)
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#define FEC_MMFR_TA(x) (((x)&0x03)<<16)
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#define FEC_MMFR_TA_10 (0x00020000)
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/* Bit definitions and macros for FEC_MSCR */
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#define FEC_MSCR_DIS_PREAMBLE (0x00000080)
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#define FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<1)
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/* Bit definitions and macros for FEC_MIBC */
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#define FEC_MIBC_MIB_DISABLE (0x80000000)
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#define FEC_MIBC_MIB_IDLE (0x40000000)
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/* Bit definitions and macros for FEC_RCR */
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#define FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<16)
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#define FEC_RCR_FCE (0x00000020)
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#define FEC_RCR_BC_REJ (0x00000010)
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#define FEC_RCR_PROM (0x00000008)
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#define FEC_RCR_MII_MODE (0x00000004)
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#define FEC_RCR_DRT (0x00000002)
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#define FEC_RCR_LOOP (0x00000001)
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/* Bit definitions and macros for FEC_TCR */
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#define FEC_TCR_RFC_PAUSE (0x00000010)
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#define FEC_TCR_TFC_PAUSE (0x00000008)
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#define FEC_TCR_FDEN (0x00000004)
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#define FEC_TCR_HBC (0x00000002)
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#define FEC_TCR_GTS (0x00000001)
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/* Bit definitions and macros for FEC_PAUR */
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#define FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<16)
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#define FEC_PAUR_TYPE(x) ((x)&0xFFFF)
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/* Bit definitions and macros for FEC_OPD */
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#define FEC_OPD_PAUSE_DUR(x) (((x)&0x0000FFFF)<<0)
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#define FEC_OPD_OPCODE(x) (((x)&0x0000FFFF)<<16)
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/* Bit definitions and macros for FEC_TFWR */
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#define FEC_TFWR_X_WMRK(x) ((x)&0x03)
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#define FEC_TFWR_X_WMRK_64 (0x01)
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#define FEC_TFWR_X_WMRK_128 (0x02)
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#define FEC_TFWR_X_WMRK_192 (0x03)
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/* Bit definitions and macros for FEC_FRBR */
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#define FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<2)
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/* Bit definitions and macros for FEC_FRSR */
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#define FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<2)
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/* Bit definitions and macros for FEC_ERDSR */
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#define FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<2)
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/* Bit definitions and macros for FEC_ETDSR */
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#define FEC_ETDSR_X_DES_START(x) (((x)&0x3FFFFFFF)<<2)
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/* Bit definitions and macros for FEC_EMRBR */
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#define FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<4)
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#define FEC_RESET_DELAY 100
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#define FEC_RX_TOUT 100
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#endif /* fec_h */
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