upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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867 lines
26 KiB
867 lines
26 KiB
/*-----------------------------------------------------------------------------+
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*
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* This source code has been made available to you by IBM on an AS-IS
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* basis. Anyone receiving this source is licensed under IBM
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* copyrights to use it in any way he or she deems fit, including
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* copying it, modifying it, compiling it, and redistributing it either
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* with or without modifications. No license under IBM patents or
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* patent applications is to be implied by the copyright license.
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*
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* Any user of this software should understand that IBM cannot provide
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* technical support for this software and will not be responsible for
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* any consequences resulting from the use of this software.
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*
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* Any person who transfers this source code or any derivative work
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* must include the IBM copyright notice, this paragraph, and the
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* preceding two paragraphs in the transferred software.
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*
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* COPYRIGHT I B M CORPORATION 1995
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* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
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*-----------------------------------------------------------------------------*/
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/*-----------------------------------------------------------------------------+
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*
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* File Name: enetemac.c
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*
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* Function: Device driver for the ethernet EMAC3 macro on the 405GP.
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*
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* Author: Mark Wisner
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*
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* Change Activity-
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*
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* Date Description of Change BY
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* --------- --------------------- ---
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* 05-May-99 Created MKW
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* 27-Jun-99 Clean up JWB
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* 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
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* 29-Jul-99 Added Full duplex support MKW
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* 06-Aug-99 Changed names for Mal CR reg MKW
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* 23-Aug-99 Turned off SYE when running at 10Mbs MKW
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* 24-Aug-99 Marked descriptor empty after call_xlc MKW
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* 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
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* to avoid chaining maximum sized packets. Push starting
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* RX descriptor address up to the next cache line boundary.
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* 16-Jan-00 Added support for booting with IP of 0x0 MKW
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* 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
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* EMAC_RXM register. JWB
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* 12-Mar-01 anne-sophie.harnois@nextream.fr
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* - Variables are compatible with those already defined in
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* include/net.h
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* - Receive buffer descriptor ring is used to send buffers
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* to the user
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* - Info print about send/received/handled packet number if
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* INFO_405_ENET is set
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* 17-Apr-01 stefan.roese@esd-electronics.com
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* - MAL reset in "eth_halt" included
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* - Enet speed and duplex output now in one line
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* 08-May-01 stefan.roese@esd-electronics.com
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* - MAL error handling added (eth_init called again)
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* 13-Nov-01 stefan.roese@esd-electronics.com
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* - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex
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* 04-Jan-02 stefan.roese@esd-electronics.com
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* - Wait for PHY auto negotiation to complete added
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* 06-Feb-02 stefan.roese@esd-electronics.com
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* - Bug fixed in waiting for auto negotiation to complete
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* 26-Feb-02 stefan.roese@esd-electronics.com
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* - rx and tx buffer descriptors now allocated (no fixed address
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* used anymore)
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* 17-Jun-02 stefan.roese@esd-electronics.com
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* - MAL error debug printf 'M' removed (rx de interrupt may
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* occur upon many incoming packets with only 4 rx buffers).
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*-----------------------------------------------------------------------------*/
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#include <common.h>
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#include <asm/processor.h>
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#include <ppc4xx.h>
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#include <commproc.h>
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#include <405gp_enet.h>
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#include <405_mal.h>
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#include <miiphy.h>
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#include <net.h>
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#include <malloc.h>
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#include "vecnum.h"
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#if defined(CONFIG_405GP) || defined(CONFIG_440)
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#define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
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#define PHY_AUTONEGOTIATE_TIMEOUT 2000 /* 2000 ms autonegotiate timeout */
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#define NUM_TX_BUFF 1
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/* AS.HARNOIS
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* Use PKTBUFSRX (include/net.h) instead of setting NUM_RX_BUFF again
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* These both variables are used to define the same thing!
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* #define NUM_RX_BUFF 4
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*/
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#define NUM_RX_BUFF PKTBUFSRX
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/* Ethernet Transmit and Receive Buffers */
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/* AS.HARNOIS
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* In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
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* PKTSIZE and PKTSIZE_ALIGN (include/net.h)
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*/
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#define ENET_MAX_MTU PKTSIZE
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#define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
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static char *txbuf_ptr;
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/* define the number of channels implemented */
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#define EMAC_RXCHL 1
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#define EMAC_TXCHL 1
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/*-----------------------------------------------------------------------------+
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* Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
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* Interrupt Controller).
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*-----------------------------------------------------------------------------*/
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#define MAL_UIC_ERR ( UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
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#define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
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#define EMAC_UIC_DEF UIC_ENET
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/*-----------------------------------------------------------------------------+
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* Global variables. TX and RX descriptors and buffers.
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*-----------------------------------------------------------------------------*/
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static volatile mal_desc_t *tx;
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static volatile mal_desc_t *rx;
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static mal_desc_t *alloc_tx_buf = NULL;
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static mal_desc_t *alloc_rx_buf = NULL;
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/* IER globals */
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static unsigned long emac_ier;
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static unsigned long mal_ier;
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/* Statistic Areas */
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#define MAX_ERR_LOG 10
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struct emac_stats {
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int data_len_err;
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int rx_frames;
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int rx;
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int rx_prot_err;
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};
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static struct stats { /* Statistic Block */
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struct emac_stats emac;
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int int_err;
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short tx_err_log[MAX_ERR_LOG];
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short rx_err_log[MAX_ERR_LOG];
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} stats;
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static int first_init = 0;
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static int tx_err_index = 0; /* Transmit Error Index for tx_err_log */
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static int rx_err_index = 0; /* Receive Error Index for rx_err_log */
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static int rx_slot = 0; /* MAL Receive Slot */
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static int rx_i_index = 0; /* Receive Interrupt Queue Index */
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static int rx_u_index = 0; /* Receive User Queue Index */
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static int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
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static int tx_slot = 0; /* MAL Transmit Slot */
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static int tx_i_index = 0; /* Transmit Interrupt Queue Index */
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static int tx_u_index = 0; /* Transmit User Queue Index */
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static int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
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#undef INFO_405_ENET 1
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#ifdef INFO_405_ENET
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static int packetSent = 0;
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static int packetReceived = 0;
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static int packetHandled = 0;
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#endif
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static char emac_hwd_addr[ENET_ADDR_LENGTH];
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static bd_t *bis_save = NULL; /* for eth_init upon mal error */
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static int is_receiving = 0; /* sync with eth interrupt */
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static int print_speed = 1; /* print speed message upon start */
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static void enet_rcv (unsigned long malisr);
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/*-----------------------------------------------------------------------------+
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* Prototypes and externals.
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*-----------------------------------------------------------------------------*/
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void mal_err (unsigned long isr, unsigned long uic, unsigned long mal_def,
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unsigned long mal_errr);
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void emac_err (unsigned long isr);
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void eth_halt (void)
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{
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mtdcr (malier, 0x00000000); /* disable mal interrupts */
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out32 (EMAC_IER, 0x00000000); /* disable emac interrupts */
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/* 1st reset MAL */
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mtdcr (malmcr, MAL_CR_MMSR);
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/* wait for reset */
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while (mfdcr (malmcr) & MAL_CR_MMSR) {
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};
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/* EMAC RESET */
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out32 (EMAC_M0, EMAC_M0_SRST);
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print_speed = 1; /* print speed message again next time */
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}
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int eth_init (bd_t * bis)
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{
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int i;
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unsigned long reg;
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unsigned long msr;
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unsigned long speed;
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unsigned long duplex;
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unsigned mode_reg;
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unsigned short reg_short;
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msr = mfmsr ();
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mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
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#ifdef INFO_405_ENET
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/* AS.HARNOIS
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* We should have :
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* packetHandled <= packetReceived <= packetHandled+PKTBUFSRX
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* In the most cases packetHandled = packetReceived, but it
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* is possible that new packets (without relationship with
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* current transfer) have got the time to arrived before
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* netloop calls eth_halt
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*/
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printf ("About preceeding transfer:\n"
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"- Sent packet number %d\n"
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"- Received packet number %d\n"
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"- Handled packet number %d\n",
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packetSent, packetReceived, packetHandled);
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packetSent = 0;
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packetReceived = 0;
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packetHandled = 0;
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#endif
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/* MAL RESET */
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mtdcr (malmcr, MAL_CR_MMSR);
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/* wait for reset */
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while (mfdcr (malmcr) & MAL_CR_MMSR) {
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};
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tx_err_index = 0; /* Transmit Error Index for tx_err_log */
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rx_err_index = 0; /* Receive Error Index for rx_err_log */
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rx_slot = 0; /* MAL Receive Slot */
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rx_i_index = 0; /* Receive Interrupt Queue Index */
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rx_u_index = 0; /* Receive User Queue Index */
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tx_slot = 0; /* MAL Transmit Slot */
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tx_i_index = 0; /* Transmit Interrupt Queue Index */
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tx_u_index = 0; /* Transmit User Queue Index */
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#if defined(CONFIG_440)
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/* set RMII mode */
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out32 (ZMII_FER, ZMII_RMII | ZMII_MDI0);
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#endif /* CONFIG_440 */
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/* EMAC RESET */
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out32 (EMAC_M0, EMAC_M0_SRST);
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/* wait for PHY to complete auto negotiation */
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reg_short = 0;
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#ifndef CONFIG_CS8952_PHY
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miiphy_read (CONFIG_PHY_ADDR, PHY_BMSR, ®_short);
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/*
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* Wait if PHY is able of autonegotiation and autonegotiation is not complete
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*/
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if ((reg_short & PHY_BMSR_AUTN_ABLE)
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&& !(reg_short & PHY_BMSR_AUTN_COMP)) {
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puts ("Waiting for PHY auto negotiation to complete");
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i = 0;
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while (!(reg_short & PHY_BMSR_AUTN_COMP)) {
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if ((i++ % 100) == 0)
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putc ('.');
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udelay (10000); /* 10 ms */
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miiphy_read (CONFIG_PHY_ADDR, PHY_BMSR, ®_short);
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/*
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* Timeout reached ?
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*/
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if (i * 10 > PHY_AUTONEGOTIATE_TIMEOUT) {
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puts (" TIMEOUT !\n");
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break;
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}
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}
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puts (" done\n");
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udelay (500000); /* another 500 ms (results in faster booting) */
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}
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#endif
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speed = miiphy_speed (CONFIG_PHY_ADDR);
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duplex = miiphy_duplex (CONFIG_PHY_ADDR);
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if (print_speed) {
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print_speed = 0;
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printf ("ENET Speed is %d Mbps - %s duplex connection\n",
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(int) speed, (duplex == HALF) ? "HALF" : "FULL");
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}
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/* set the Mal configuration reg */
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#if defined(CONFIG_440)
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/* Errata 1.12: MAL_1 -- Disable MAL bursting */
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if( get_pvr() == PVR_440GP_RB )
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mtdcr (malmcr, MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
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else
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#else
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mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
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#endif
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/* Free "old" buffers */
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if (alloc_tx_buf) free(alloc_tx_buf);
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if (alloc_rx_buf) free(alloc_rx_buf);
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/*
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* Malloc MAL buffer desciptors, make sure they are
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* aligned on cache line boundary size
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* (401/403/IOP480 = 16, 405 = 32)
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* and doesn't cross cache block boundaries.
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*/
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alloc_tx_buf = (mal_desc_t *)malloc((sizeof(mal_desc_t) * NUM_TX_BUFF) +
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((2 * CFG_CACHELINE_SIZE) - 2));
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if (((int)alloc_tx_buf & CACHELINE_MASK) != 0) {
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tx = (mal_desc_t *)((int)alloc_tx_buf + CFG_CACHELINE_SIZE -
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((int)alloc_tx_buf & CACHELINE_MASK));
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} else {
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tx = alloc_tx_buf;
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}
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alloc_rx_buf = (mal_desc_t *)malloc((sizeof(mal_desc_t) * NUM_RX_BUFF) +
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((2 * CFG_CACHELINE_SIZE) - 2));
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if (((int)alloc_rx_buf & CACHELINE_MASK) != 0) {
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rx = (mal_desc_t *)((int)alloc_rx_buf + CFG_CACHELINE_SIZE -
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((int)alloc_rx_buf & CACHELINE_MASK));
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} else {
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rx = alloc_rx_buf;
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}
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for (i = 0; i < NUM_TX_BUFF; i++) {
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tx[i].ctrl = 0;
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tx[i].data_len = 0;
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if (first_init == 0)
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txbuf_ptr = (char *) malloc (ENET_MAX_MTU_ALIGNED);
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tx[i].data_ptr = txbuf_ptr;
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if ((NUM_TX_BUFF - 1) == i)
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tx[i].ctrl |= MAL_TX_CTRL_WRAP;
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tx_run[i] = -1;
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#if 0
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printf ("TX_BUFF %d @ 0x%08lx\n", i, (ulong) tx[i].data_ptr);
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#endif
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}
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for (i = 0; i < NUM_RX_BUFF; i++) {
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rx[i].ctrl = 0;
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rx[i].data_len = 0;
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/* rx[i].data_ptr = (char *) &rx_buff[i]; */
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rx[i].data_ptr = (char *) NetRxPackets[i];
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if ((NUM_RX_BUFF - 1) == i)
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rx[i].ctrl |= MAL_RX_CTRL_WRAP;
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rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
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rx_ready[i] = -1;
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#if 0
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printf ("RX_BUFF %d @ 0x%08lx\n", i, (ulong) rx[i].data_ptr);
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#endif
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}
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memcpy (emac_hwd_addr, bis->bi_enetaddr, ENET_ADDR_LENGTH);
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reg = 0x00000000;
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reg |= emac_hwd_addr[0]; /* set high address */
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reg = reg << 8;
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reg |= emac_hwd_addr[1];
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out32 (EMAC_IAH, reg);
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reg = 0x00000000;
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reg |= emac_hwd_addr[2]; /* set low address */
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reg = reg << 8;
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reg |= emac_hwd_addr[3];
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reg = reg << 8;
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reg |= emac_hwd_addr[4];
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reg = reg << 8;
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reg |= emac_hwd_addr[5];
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out32 (EMAC_IAL, reg);
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|
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/* setup MAL tx & rx channel pointers */
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mtdcr (maltxctp0r, tx);
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mtdcr (malrxctp0r, rx);
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|
|
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/* Reset transmit and receive channels */
|
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mtdcr (malrxcarr, 0x80000000); /* 2 channels */
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mtdcr (maltxcarr, 0x80000000); /* 2 channels */
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|
|
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/* Enable MAL transmit and receive channels */
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mtdcr (maltxcasr, 0x80000000); /* 1 channel */
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mtdcr (malrxcasr, 0x80000000); /* 1 channel */
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|
|
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/* set RX buffer size */
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mtdcr (malrcbs0, ENET_MAX_MTU_ALIGNED / 16);
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|
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/* set transmit enable & receive enable */
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out32 (EMAC_M0, EMAC_M0_TXE | EMAC_M0_RXE);
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|
|
|
/* set receive fifo to 4k and tx fifo to 2k */
|
|
mode_reg = EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K;
|
|
|
|
/* set speed */
|
|
if (speed == _100BASET)
|
|
mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST;
|
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else
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|
mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
|
|
if (duplex == FULL)
|
|
mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST;
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|
|
|
out32 (EMAC_M1, mode_reg);
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|
|
|
/* Enable broadcast and indvidual address */
|
|
out32 (EMAC_RXM, EMAC_RMR_BAE | EMAC_RMR_IAE
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|
/*| EMAC_RMR_ARRP| EMAC_RMR_SFCS | EMAC_RMR_SP */ );
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|
|
|
/* we probably need to set the tx mode1 reg? maybe at tx time */
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|
|
|
/* set transmit request threshold register */
|
|
out32 (EMAC_TRTR, 0x18000000); /* 256 byte threshold */
|
|
|
|
/* set receive low/high water mark register */
|
|
#if defined(CONFIG_440)
|
|
/* 440GP has a 64 byte burst length */
|
|
out32 (EMAC_RX_HI_LO_WMARK, 0x80009000);
|
|
out32 (EMAC_TXM1, 0xf8640000);
|
|
#else /* CONFIG_440 */
|
|
/* 405s have a 16 byte burst length */
|
|
out32 (EMAC_RX_HI_LO_WMARK, 0x0f002000);
|
|
#endif /* CONFIG_440 */
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|
|
/* Frame gap set */
|
|
out32 (EMAC_I_FRAME_GAP_REG, 0x00000008);
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|
|
|
if (first_init == 0) {
|
|
/*
|
|
* Connect interrupt service routines
|
|
*/
|
|
irq_install_handler (VECNUM_EWU0, (interrupt_handler_t *) enetInt, NULL);
|
|
irq_install_handler (VECNUM_MS, (interrupt_handler_t *) enetInt, NULL);
|
|
irq_install_handler (VECNUM_MTE, (interrupt_handler_t *) enetInt, NULL);
|
|
irq_install_handler (VECNUM_MRE, (interrupt_handler_t *) enetInt, NULL);
|
|
irq_install_handler (VECNUM_TXDE, (interrupt_handler_t *) enetInt, NULL);
|
|
irq_install_handler (VECNUM_RXDE, (interrupt_handler_t *) enetInt, NULL);
|
|
irq_install_handler (VECNUM_ETH0, (interrupt_handler_t *) enetInt, NULL);
|
|
}
|
|
|
|
/* set up interrupt handler */
|
|
/* setup interrupt controler to take interrupts from the MAL &
|
|
EMAC */
|
|
mtdcr (uicsr, 0xffffffff); /* clear pending interrupts */
|
|
mtdcr (uicer, mfdcr (uicer) | MAL_UIC_DEF | EMAC_UIC_DEF);
|
|
|
|
/* set the MAL IER ??? names may change with new spec ??? */
|
|
mal_ier = MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | MAL_IER_OPBE |
|
|
MAL_IER_PLBE;
|
|
mtdcr (malesr, 0xffffffff); /* clear pending interrupts */
|
|
mtdcr (maltxdeir, 0xffffffff); /* clear pending interrupts */
|
|
mtdcr (malrxdeir, 0xffffffff); /* clear pending interrupts */
|
|
mtdcr (malier, mal_ier);
|
|
|
|
/* Set EMAC IER */
|
|
emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS |
|
|
EMAC_ISR_PTLE | EMAC_ISR_ORE | EMAC_ISR_IRE;
|
|
if (speed == _100BASET)
|
|
emac_ier = emac_ier | EMAC_ISR_SYE;
|
|
|
|
out32 (EMAC_ISR, 0xffffffff); /* clear pending interrupts */
|
|
out32 (EMAC_IER, emac_ier);
|
|
|
|
mtmsr (msr); /* enable interrupts again */
|
|
|
|
bis_save = bis;
|
|
first_init = 1;
|
|
|
|
return (0);
|
|
}
|
|
|
|
|
|
int eth_send (volatile void *ptr, int len)
|
|
{
|
|
struct enet_frame *ef_ptr;
|
|
ulong time_start, time_now;
|
|
unsigned long temp_txm0;
|
|
|
|
ef_ptr = (struct enet_frame *) ptr;
|
|
|
|
/*-----------------------------------------------------------------------+
|
|
* Copy in our address into the frame.
|
|
*-----------------------------------------------------------------------*/
|
|
(void) memcpy (ef_ptr->source_addr, emac_hwd_addr, ENET_ADDR_LENGTH);
|
|
|
|
/*-----------------------------------------------------------------------+
|
|
* If frame is too long or too short, modify length.
|
|
*-----------------------------------------------------------------------*/
|
|
if (len > ENET_MAX_MTU)
|
|
len = ENET_MAX_MTU;
|
|
|
|
/* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
|
|
memcpy ((void *) txbuf_ptr, (const void *) ptr, len);
|
|
|
|
/*-----------------------------------------------------------------------+
|
|
* set TX Buffer busy, and send it
|
|
*-----------------------------------------------------------------------*/
|
|
tx[tx_slot].ctrl = (MAL_TX_CTRL_LAST |
|
|
EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
|
|
~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
|
|
if ((NUM_TX_BUFF - 1) == tx_slot)
|
|
tx[tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
|
|
|
|
tx[tx_slot].data_len = (short) len;
|
|
tx[tx_slot].ctrl |= MAL_TX_CTRL_READY;
|
|
|
|
__asm__ volatile ("eieio");
|
|
out32 (EMAC_TXM0, in32 (EMAC_TXM0) | EMAC_TXM0_GNP0);
|
|
#ifdef INFO_405_ENET
|
|
packetSent++;
|
|
#endif
|
|
|
|
/*-----------------------------------------------------------------------+
|
|
* poll unitl the packet is sent and then make sure it is OK
|
|
*-----------------------------------------------------------------------*/
|
|
time_start = get_timer (0);
|
|
while (1) {
|
|
temp_txm0 = in32 (EMAC_TXM0);
|
|
/* loop until either TINT turns on or 3 seconds elapse */
|
|
if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) {
|
|
/* transmit is done, so now check for errors
|
|
* If there is an error, an interrupt should
|
|
* happen when we return
|
|
*/
|
|
time_now = get_timer (0);
|
|
if ((time_now - time_start) > 3000) {
|
|
return (-1);
|
|
}
|
|
} else {
|
|
return (0);
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
#if defined(CONFIG_440)
|
|
/*-----------------------------------------------------------------------------+
|
|
| EnetInt.
|
|
| EnetInt is the interrupt handler. It will determine the
|
|
| cause of the interrupt and call the apporpriate servive
|
|
| routine.
|
|
+-----------------------------------------------------------------------------*/
|
|
int enetInt ()
|
|
{
|
|
int serviced;
|
|
int rc = -1; /* default to not us */
|
|
unsigned long mal_isr;
|
|
unsigned long emac_isr = 0;
|
|
unsigned long mal_rx_eob;
|
|
unsigned long my_uic0msr, my_uic1msr;
|
|
|
|
/* enter loop that stays in interrupt code until nothing to service */
|
|
do {
|
|
serviced = 0;
|
|
|
|
my_uic0msr = mfdcr (uic0msr);
|
|
my_uic1msr = mfdcr (uic1msr);
|
|
|
|
if (!(my_uic0msr & UIC_MRE)
|
|
&& !(my_uic1msr & (UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE))) {
|
|
/* not for us */
|
|
return (rc);
|
|
}
|
|
|
|
/* get and clear controller status interrupts */
|
|
/* look at Mal and EMAC interrupts */
|
|
if ((my_uic0msr & UIC_MRE)
|
|
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
|
|
/* we have a MAL interrupt */
|
|
mal_isr = mfdcr (malesr);
|
|
/* look for mal error */
|
|
if (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE)) {
|
|
mal_err (mal_isr, my_uic0msr, MAL_UIC_DEF, MAL_UIC_ERR);
|
|
serviced = 1;
|
|
rc = 0;
|
|
}
|
|
}
|
|
if (UIC_ETH0 & my_uic1msr) { /* look for EMAC errors */
|
|
emac_isr = in32 (EMAC_ISR);
|
|
if ((emac_ier & emac_isr) != 0) {
|
|
emac_err (emac_isr);
|
|
serviced = 1;
|
|
rc = 0;
|
|
}
|
|
}
|
|
if ((emac_ier & emac_isr)
|
|
|| (my_uic1msr & (UIC_MS | UIC_MTDE | UIC_MRDE))) {
|
|
mtdcr (uic0sr, UIC_MRE); /* Clear */
|
|
mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
|
|
return (rc); /* we had errors so get out */
|
|
}
|
|
|
|
/* handle MAL RX EOB interupt from a receive */
|
|
/* check for EOB on valid channels */
|
|
if (my_uic0msr & UIC_MRE) {
|
|
mal_rx_eob = mfdcr (malrxeobisr);
|
|
if ((mal_rx_eob & 0x80000000) != 0) { /* call emac routine for channel 0 */
|
|
/* clear EOB
|
|
mtdcr(malrxeobisr, mal_rx_eob); */
|
|
enet_rcv (emac_isr);
|
|
/* indicate that we serviced an interrupt */
|
|
serviced = 1;
|
|
rc = 0;
|
|
}
|
|
}
|
|
mtdcr (uic0sr, UIC_MRE); /* Clear */
|
|
mtdcr (uic1sr, UIC_ETH0 | UIC_MS | UIC_MTDE | UIC_MRDE); /* Clear */
|
|
} while (serviced);
|
|
|
|
return (rc);
|
|
}
|
|
#else /* CONFIG_440 */
|
|
/*-----------------------------------------------------------------------------+
|
|
* EnetInt.
|
|
* EnetInt is the interrupt handler. It will determine the
|
|
* cause of the interrupt and call the apporpriate servive
|
|
* routine.
|
|
*-----------------------------------------------------------------------------*/
|
|
int enetInt ()
|
|
{
|
|
int serviced;
|
|
int rc = -1; /* default to not us */
|
|
unsigned long mal_isr;
|
|
unsigned long emac_isr = 0;
|
|
unsigned long mal_rx_eob;
|
|
unsigned long my_uicmsr;
|
|
|
|
/* enter loop that stays in interrupt code until nothing to service */
|
|
do {
|
|
serviced = 0;
|
|
|
|
my_uicmsr = mfdcr (uicmsr);
|
|
if ((my_uicmsr & (MAL_UIC_DEF | EMAC_UIC_DEF)) == 0) { /* not for us */
|
|
return (rc);
|
|
}
|
|
|
|
|
|
/* get and clear controller status interrupts */
|
|
/* look at Mal and EMAC interrupts */
|
|
if ((MAL_UIC_DEF & my_uicmsr) != 0) { /* we have a MAL interrupt */
|
|
mal_isr = mfdcr (malesr);
|
|
/* look for mal error */
|
|
if ((my_uicmsr & MAL_UIC_ERR) != 0) {
|
|
mal_err (mal_isr, my_uicmsr, MAL_UIC_DEF, MAL_UIC_ERR);
|
|
serviced = 1;
|
|
rc = 0;
|
|
}
|
|
}
|
|
if ((EMAC_UIC_DEF & my_uicmsr) != 0) { /* look for EMAC errors */
|
|
emac_isr = in32 (EMAC_ISR);
|
|
if ((emac_ier & emac_isr) != 0) {
|
|
emac_err (emac_isr);
|
|
serviced = 1;
|
|
rc = 0;
|
|
}
|
|
}
|
|
if (((emac_ier & emac_isr) != 0) | ((MAL_UIC_ERR & my_uicmsr) != 0)) {
|
|
mtdcr (uicsr, MAL_UIC_DEF | EMAC_UIC_DEF); /* Clear */
|
|
return (rc); /* we had errors so get out */
|
|
}
|
|
|
|
|
|
/* handle MAL RX EOB interupt from a receive */
|
|
/* check for EOB on valid channels */
|
|
if ((my_uicmsr & UIC_MAL_RXEOB) != 0) {
|
|
mal_rx_eob = mfdcr (malrxeobisr);
|
|
if ((mal_rx_eob & 0x80000000) != 0) { /* call emac routine for channel 0 */
|
|
/* clear EOB
|
|
mtdcr(malrxeobisr, mal_rx_eob); */
|
|
enet_rcv (emac_isr);
|
|
/* indicate that we serviced an interrupt */
|
|
serviced = 1;
|
|
rc = 0;
|
|
}
|
|
}
|
|
mtdcr (uicsr, MAL_UIC_DEF | EMAC_UIC_DEF); /* Clear */
|
|
}
|
|
while (serviced);
|
|
|
|
return (rc);
|
|
}
|
|
#endif /* CONFIG_440 */
|
|
|
|
/*-----------------------------------------------------------------------------+
|
|
* MAL Error Routine
|
|
*-----------------------------------------------------------------------------*/
|
|
void mal_err (unsigned long isr, unsigned long uic, unsigned long maldef,
|
|
unsigned long mal_errr)
|
|
{
|
|
mtdcr (malesr, isr); /* clear interrupt */
|
|
|
|
/* clear DE interrupt */
|
|
mtdcr (maltxdeir, 0xC0000000);
|
|
mtdcr (malrxdeir, 0x80000000);
|
|
|
|
#if 1 /*sr */
|
|
printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n",
|
|
isr, uic, maldef, mal_errr);
|
|
#else
|
|
#if 0
|
|
/*
|
|
* MAL error is RX DE error (out of rx buffers)! This is OK here, upon
|
|
* many incoming packets with only 4 rx buffers.
|
|
*/
|
|
printf ("M"); /* just to see something upon mal error */
|
|
#endif
|
|
#endif /*sr */
|
|
|
|
eth_init (bis_save); /* start again... */
|
|
}
|
|
|
|
/*-----------------------------------------------------------------------------+
|
|
* EMAC Error Routine
|
|
*-----------------------------------------------------------------------------*/
|
|
void emac_err (unsigned long isr)
|
|
{
|
|
printf ("EMAC error occured.... ISR = %lx\n", isr);
|
|
out32 (EMAC_ISR, isr);
|
|
}
|
|
|
|
/*-----------------------------------------------------------------------------+
|
|
* enet_rcv() handles the ethernet receive data
|
|
*-----------------------------------------------------------------------------*/
|
|
static void enet_rcv (unsigned long malisr)
|
|
{
|
|
struct enet_frame *ef_ptr;
|
|
unsigned long data_len;
|
|
unsigned long rx_eob_isr;
|
|
|
|
int handled = 0;
|
|
int i;
|
|
int loop_count = 0;
|
|
|
|
rx_eob_isr = mfdcr (malrxeobisr);
|
|
if ((0x80000000 >> (EMAC_RXCHL - 1)) & rx_eob_isr) {
|
|
/* clear EOB */
|
|
mtdcr (malrxeobisr, rx_eob_isr);
|
|
|
|
/* EMAC RX done */
|
|
while (1) { /* do all */
|
|
i = rx_slot;
|
|
|
|
if ((MAL_RX_CTRL_EMPTY & rx[i].ctrl)
|
|
|| (loop_count >= NUM_RX_BUFF))
|
|
break;
|
|
loop_count++;
|
|
rx_slot++;
|
|
if (NUM_RX_BUFF == rx_slot)
|
|
rx_slot = 0;
|
|
handled++;
|
|
data_len = (unsigned long) rx[i].data_len; /* Get len */
|
|
if (data_len) {
|
|
if (data_len > ENET_MAX_MTU) /* Check len */
|
|
data_len = 0;
|
|
else {
|
|
if (EMAC_RX_ERRORS & rx[i].ctrl) { /* Check Errors */
|
|
data_len = 0;
|
|
stats.rx_err_log[rx_err_index] = rx[i].ctrl;
|
|
rx_err_index++;
|
|
if (rx_err_index == MAX_ERR_LOG)
|
|
rx_err_index = 0;
|
|
} /* emac_erros */
|
|
} /* data_len < max mtu */
|
|
} /* if data_len */
|
|
if (!data_len) { /* no data */
|
|
rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
|
|
|
|
stats.emac.data_len_err++; /* Error at Rx */
|
|
}
|
|
|
|
/* !data_len */
|
|
/* AS.HARNOIS */
|
|
/* Check if user has already eaten buffer */
|
|
/* if not => ERROR */
|
|
else if (rx_ready[rx_i_index] != -1) {
|
|
if (is_receiving)
|
|
printf ("ERROR : Receive buffers are full!\n");
|
|
break;
|
|
} else {
|
|
stats.emac.rx_frames++;
|
|
stats.emac.rx += data_len;
|
|
ef_ptr = (struct enet_frame *) rx[i].data_ptr;
|
|
#ifdef INFO_405_ENET
|
|
packetReceived++;
|
|
#endif
|
|
/* AS.HARNOIS
|
|
* use ring buffer
|
|
*/
|
|
rx_ready[rx_i_index] = i;
|
|
rx_i_index++;
|
|
if (NUM_RX_BUFF == rx_i_index)
|
|
rx_i_index = 0;
|
|
|
|
/* printf("X"); /|* test-only *|/ */
|
|
|
|
/* AS.HARNOIS
|
|
* free receive buffer only when
|
|
* buffer has been handled (eth_rx)
|
|
rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
|
|
*/
|
|
} /* if data_len */
|
|
} /* while */
|
|
} /* if EMACK_RXCHL */
|
|
}
|
|
|
|
|
|
int eth_rx (void)
|
|
{
|
|
int length;
|
|
int user_index;
|
|
unsigned long msr;
|
|
|
|
is_receiving = 1; /* tell driver */
|
|
|
|
for (;;) {
|
|
/* AS.HARNOIS
|
|
* use ring buffer and
|
|
* get index from rx buffer desciptor queue
|
|
*/
|
|
user_index = rx_ready[rx_u_index];
|
|
if (user_index == -1) {
|
|
length = -1;
|
|
break; /* nothing received - leave for() loop */
|
|
}
|
|
|
|
msr = mfmsr ();
|
|
mtmsr (msr & ~(MSR_EE));
|
|
|
|
length = rx[user_index].data_len;
|
|
|
|
/* Pass the packet up to the protocol layers. */
|
|
/* NetReceive(NetRxPackets[rxIdx], length - 4); */
|
|
/* NetReceive(NetRxPackets[i], length); */
|
|
NetReceive (NetRxPackets[user_index], length - 4);
|
|
/* Free Recv Buffer */
|
|
rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
|
|
/* Free rx buffer descriptor queue */
|
|
rx_ready[rx_u_index] = -1;
|
|
rx_u_index++;
|
|
if (NUM_RX_BUFF == rx_u_index)
|
|
rx_u_index = 0;
|
|
|
|
#ifdef INFO_405_ENET
|
|
packetHandled++;
|
|
#endif
|
|
|
|
mtmsr (msr); /* Enable IRQ's */
|
|
}
|
|
|
|
is_receiving = 0; /* tell driver */
|
|
|
|
return length;
|
|
}
|
|
|
|
#endif /* CONFIG_405GP */
|
|
|