upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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164 lines
3.6 KiB
164 lines
3.6 KiB
/*
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* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include "../init.h"
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#include "../sc-regs.h"
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#include "../sg-regs.h"
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#undef DPLL_SSC_RATE_1PER
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static int dpll_init(unsigned int dram_freq)
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{
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u32 tmp;
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/*
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* Set Frequency
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* Set 0xc(1600MHz)/0xd(1333MHz)/0xe(1066MHz)
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* to FOUT ( DPLLCTRL.bit[29:20] )
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*/
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tmp = readl(SC_DPLLCTRL);
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tmp &= ~(0x000f0000);
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switch (dram_freq) {
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case 1333:
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tmp |= 0x000d0000;
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break;
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case 1600:
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tmp |= 0x000c0000;
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break;
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default:
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pr_err("Unsupported frequency");
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return -EINVAL;
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}
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/*
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* Set Moduration rate
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* Set 0x0(1%)/0x1(2%) to SSC_RATE(DPLLCTRL.bit[15])
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*/
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#if defined(DPLL_SSC_RATE_1PER)
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tmp &= ~0x00008000;
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#else
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tmp |= 0x00008000;
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#endif
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writel(tmp, SC_DPLLCTRL);
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tmp = readl(SC_DPLLCTRL2);
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tmp |= SC_DPLLCTRL2_NRSTDS;
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writel(tmp, SC_DPLLCTRL2);
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return 0;
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}
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static void vpll_init(void)
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{
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u32 tmp, clk_mode_axosel;
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/* Set VPLL27A & VPLL27B */
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tmp = readl(SG_PINMON0);
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clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
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/* 25MHz or 6.25MHz is default for Pro4R, no need to set VPLLA/B */
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if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
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clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ)
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return;
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/* Disable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
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tmp = readl(SC_VPLL27ACTRL);
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tmp |= 0x00000001;
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writel(tmp, SC_VPLL27ACTRL);
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tmp = readl(SC_VPLL27BCTRL);
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tmp |= 0x00000001;
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writel(tmp, SC_VPLL27BCTRL);
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/* Unset VPLA_K_LD and VPLB_K_LD bit */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp &= ~0x10000000;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp &= ~0x10000000;
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writel(tmp, SC_VPLL27BCTRL3);
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/* Set VPLA_M and VPLB_M to 0x20 */
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tmp = readl(SC_VPLL27ACTRL2);
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tmp &= ~0x0000007f;
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tmp |= 0x00000020;
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writel(tmp, SC_VPLL27ACTRL2);
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tmp = readl(SC_VPLL27BCTRL2);
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tmp &= ~0x0000007f;
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tmp |= 0x00000020;
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writel(tmp, SC_VPLL27BCTRL2);
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if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ ||
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clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ) {
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/* Set VPLA_K and VPLB_K for AXO: 25MHz */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x00066666;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x00066666;
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writel(tmp, SC_VPLL27BCTRL3);
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} else {
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/* Set VPLA_K and VPLB_K for AXO: 24.576 MHz */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x000f5800;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp &= ~0x000fffff;
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tmp |= 0x000f5800;
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writel(tmp, SC_VPLL27BCTRL3);
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}
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/* wait 1 usec */
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udelay(1);
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/* Set VPLA_K_LD and VPLB_K_LD to load K parameters */
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tmp = readl(SC_VPLL27ACTRL3);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27ACTRL3);
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tmp = readl(SC_VPLL27BCTRL3);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27BCTRL3);
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/* Unset VPLA_SNRST and VPLB_SNRST bit */
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tmp = readl(SC_VPLL27ACTRL2);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27ACTRL2);
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tmp = readl(SC_VPLL27BCTRL2);
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tmp |= 0x10000000;
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writel(tmp, SC_VPLL27BCTRL2);
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/* Enable write protect of VPLL27ACTRL[2-7]*, VPLL27BCTRL[2-8] */
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tmp = readl(SC_VPLL27ACTRL);
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tmp &= ~0x00000001;
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writel(tmp, SC_VPLL27ACTRL);
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tmp = readl(SC_VPLL27BCTRL);
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tmp &= ~0x00000001;
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writel(tmp, SC_VPLL27BCTRL);
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}
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int ph1_pro4_pll_init(const struct uniphier_board_data *bd)
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{
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int ret;
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ret = dpll_init(bd->dram_freq);
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if (ret)
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return ret;
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vpll_init();
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/*
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* Wait 500 usec until dpll get stable
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* We wait 1 usec in vpll_init() so 1 usec can be saved here.
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*/
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udelay(499);
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return 0;
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}
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