upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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495 lines
14 KiB
495 lines
14 KiB
/*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/fsl_ddr_sdram.h>
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#include "ddr.h"
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unsigned int
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compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
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common_timing_params_t *outpdimm,
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unsigned int number_of_dimms)
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{
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unsigned int i;
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unsigned int tAAmin_ps = 0;
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unsigned int tCKmin_X_ps = 0;
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unsigned int common_caslat;
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unsigned int caslat_actual;
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unsigned int retry = 16;
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unsigned int tmp;
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const unsigned int mclk_ps = get_memory_clk_period_ps();
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/* compute the common CAS latency supported between slots */
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tmp = dimm_params[0].caslat_X;
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for (i = 1; i < number_of_dimms; i++)
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tmp &= dimm_params[i].caslat_X;
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common_caslat = tmp;
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/* compute the max tAAmin tCKmin between slots */
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for (i = 0; i < number_of_dimms; i++) {
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tAAmin_ps = max(tAAmin_ps, dimm_params[i].tAA_ps);
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tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
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}
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/* validate if the memory clk is in the range of dimms */
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if (mclk_ps < tCKmin_X_ps) {
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printf("DDR clock (MCLK cycle %u ps) is faster than "
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"the slowest DIMM(s) (tCKmin %u ps) can support.\n",
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mclk_ps, tCKmin_X_ps);
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return 1;
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}
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/* determine the acutal cas latency */
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caslat_actual = (tAAmin_ps + mclk_ps - 1) / mclk_ps;
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/* check if the dimms support the CAS latency */
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while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
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caslat_actual++;
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retry--;
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}
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/* once the caculation of caslat_actual is completed
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* we must verify that this CAS latency value does not
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* exceed tAAmax, which is 20 ns for all DDR3 speed grades
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*/
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if (caslat_actual * mclk_ps > 20000) {
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printf("The choosen cas latency %d is too large\n",
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caslat_actual);
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return 1;
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}
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outpdimm->lowest_common_SPD_caslat = caslat_actual;
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return 0;
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}
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/*
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* compute_lowest_common_dimm_parameters()
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*
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* Determine the worst-case DIMM timing parameters from the set of DIMMs
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* whose parameters have been computed into the array pointed to
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* by dimm_params.
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*/
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unsigned int
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compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
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common_timing_params_t *outpdimm,
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unsigned int number_of_dimms)
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{
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unsigned int i, j;
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unsigned int tCKmin_X_ps = 0;
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unsigned int tCKmax_ps = 0xFFFFFFFF;
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unsigned int tCKmax_max_ps = 0;
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unsigned int tRCD_ps = 0;
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unsigned int tRP_ps = 0;
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unsigned int tRAS_ps = 0;
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unsigned int tWR_ps = 0;
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unsigned int tWTR_ps = 0;
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unsigned int tRFC_ps = 0;
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unsigned int tRRD_ps = 0;
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unsigned int tRC_ps = 0;
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unsigned int refresh_rate_ps = 0;
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unsigned int tIS_ps = 0;
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unsigned int tIH_ps = 0;
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unsigned int tDS_ps = 0;
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unsigned int tDH_ps = 0;
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unsigned int tRTP_ps = 0;
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unsigned int tDQSQ_max_ps = 0;
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unsigned int tQHS_ps = 0;
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unsigned int temp1, temp2;
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unsigned int additive_latency = 0;
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#if !defined(CONFIG_FSL_DDR3)
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const unsigned int mclk_ps = get_memory_clk_period_ps();
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unsigned int lowest_good_caslat;
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unsigned int not_ok;
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debug("using mclk_ps = %u\n", mclk_ps);
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#endif
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temp1 = 0;
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for (i = 0; i < number_of_dimms; i++) {
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/*
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* If there are no ranks on this DIMM,
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* it probably doesn't exist, so skip it.
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*/
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if (dimm_params[i].n_ranks == 0) {
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temp1++;
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continue;
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}
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if (dimm_params[i].n_ranks == 4 && i != 0) {
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printf("Found Quad-rank DIMM in wrong bank, ignored."
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" Software may not run as expected.\n");
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temp1++;
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continue;
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}
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if (dimm_params[i].n_ranks == 4 && \
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CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
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printf("Found Quad-rank DIMM, not able to support.");
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temp1++;
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continue;
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}
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/*
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* Find minimum tCKmax_ps to find fastest slow speed,
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* i.e., this is the slowest the whole system can go.
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*/
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tCKmax_ps = min(tCKmax_ps, dimm_params[i].tCKmax_ps);
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/* Either find maximum value to determine slowest
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* speed, delay, time, period, etc */
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tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
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tCKmax_max_ps = max(tCKmax_max_ps, dimm_params[i].tCKmax_ps);
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tRCD_ps = max(tRCD_ps, dimm_params[i].tRCD_ps);
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tRP_ps = max(tRP_ps, dimm_params[i].tRP_ps);
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tRAS_ps = max(tRAS_ps, dimm_params[i].tRAS_ps);
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tWR_ps = max(tWR_ps, dimm_params[i].tWR_ps);
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tWTR_ps = max(tWTR_ps, dimm_params[i].tWTR_ps);
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tRFC_ps = max(tRFC_ps, dimm_params[i].tRFC_ps);
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tRRD_ps = max(tRRD_ps, dimm_params[i].tRRD_ps);
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tRC_ps = max(tRC_ps, dimm_params[i].tRC_ps);
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tIS_ps = max(tIS_ps, dimm_params[i].tIS_ps);
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tIH_ps = max(tIH_ps, dimm_params[i].tIH_ps);
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tDS_ps = max(tDS_ps, dimm_params[i].tDS_ps);
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tDH_ps = max(tDH_ps, dimm_params[i].tDH_ps);
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tRTP_ps = max(tRTP_ps, dimm_params[i].tRTP_ps);
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tQHS_ps = max(tQHS_ps, dimm_params[i].tQHS_ps);
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refresh_rate_ps = max(refresh_rate_ps,
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dimm_params[i].refresh_rate_ps);
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/*
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* Find maximum tDQSQ_max_ps to find slowest.
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*
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* FIXME: is finding the slowest value the correct
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* strategy for this parameter?
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*/
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tDQSQ_max_ps = max(tDQSQ_max_ps, dimm_params[i].tDQSQ_max_ps);
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}
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outpdimm->ndimms_present = number_of_dimms - temp1;
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if (temp1 == number_of_dimms) {
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debug("no dimms this memory controller\n");
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return 0;
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}
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outpdimm->tCKmin_X_ps = tCKmin_X_ps;
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outpdimm->tCKmax_ps = tCKmax_ps;
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outpdimm->tCKmax_max_ps = tCKmax_max_ps;
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outpdimm->tRCD_ps = tRCD_ps;
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outpdimm->tRP_ps = tRP_ps;
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outpdimm->tRAS_ps = tRAS_ps;
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outpdimm->tWR_ps = tWR_ps;
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outpdimm->tWTR_ps = tWTR_ps;
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outpdimm->tRFC_ps = tRFC_ps;
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outpdimm->tRRD_ps = tRRD_ps;
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outpdimm->tRC_ps = tRC_ps;
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outpdimm->refresh_rate_ps = refresh_rate_ps;
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outpdimm->tIS_ps = tIS_ps;
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outpdimm->tIH_ps = tIH_ps;
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outpdimm->tDS_ps = tDS_ps;
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outpdimm->tDH_ps = tDH_ps;
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outpdimm->tRTP_ps = tRTP_ps;
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outpdimm->tDQSQ_max_ps = tDQSQ_max_ps;
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outpdimm->tQHS_ps = tQHS_ps;
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/* Determine common burst length for all DIMMs. */
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temp1 = 0xff;
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for (i = 0; i < number_of_dimms; i++) {
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if (dimm_params[i].n_ranks) {
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temp1 &= dimm_params[i].burst_lengths_bitmask;
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}
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}
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outpdimm->all_DIMMs_burst_lengths_bitmask = temp1;
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/* Determine if all DIMMs registered buffered. */
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temp1 = temp2 = 0;
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for (i = 0; i < number_of_dimms; i++) {
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if (dimm_params[i].n_ranks) {
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if (dimm_params[i].registered_dimm) {
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temp1 = 1;
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printf("Detected RDIMM %s\n",
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dimm_params[i].mpart);
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} else {
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temp2 = 1;
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printf("Detected UDIMM %s\n",
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dimm_params[i].mpart);
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}
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}
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}
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outpdimm->all_DIMMs_registered = 0;
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outpdimm->all_DIMMs_unbuffered = 0;
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if (temp1 && !temp2) {
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outpdimm->all_DIMMs_registered = 1;
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} else if (!temp1 && temp2) {
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outpdimm->all_DIMMs_unbuffered = 1;
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} else {
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printf("ERROR: Mix of registered buffered and unbuffered "
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"DIMMs detected!\n");
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}
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temp1 = 0;
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if (outpdimm->all_DIMMs_registered)
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for (j = 0; j < 16; j++) {
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outpdimm->rcw[j] = dimm_params[0].rcw[j];
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for (i = 1; i < number_of_dimms; i++)
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if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
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temp1 = 1;
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break;
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}
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}
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if (temp1 != 0)
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printf("ERROR: Mix different RDIMM detected!\n");
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#if defined(CONFIG_FSL_DDR3)
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if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms))
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return 1;
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#else
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/*
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* Compute a CAS latency suitable for all DIMMs
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*
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* Strategy for SPD-defined latencies: compute only
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* CAS latency defined by all DIMMs.
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*/
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/*
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* Step 1: find CAS latency common to all DIMMs using bitwise
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* operation.
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*/
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temp1 = 0xFF;
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for (i = 0; i < number_of_dimms; i++) {
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if (dimm_params[i].n_ranks) {
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temp2 = 0;
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temp2 |= 1 << dimm_params[i].caslat_X;
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temp2 |= 1 << dimm_params[i].caslat_X_minus_1;
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temp2 |= 1 << dimm_params[i].caslat_X_minus_2;
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/*
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* FIXME: If there was no entry for X-2 (X-1) in
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* the SPD, then caslat_X_minus_2
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* (caslat_X_minus_1) contains either 255 or
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* 0xFFFFFFFF because that's what the glorious
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* __ilog2 function returns for an input of 0.
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* On 32-bit PowerPC, left shift counts with bit
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* 26 set (that the value of 255 or 0xFFFFFFFF
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* will have), cause the destination register to
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* be 0. That is why this works.
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*/
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temp1 &= temp2;
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}
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}
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/*
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* Step 2: check each common CAS latency against tCK of each
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* DIMM's SPD.
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*/
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lowest_good_caslat = 0;
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temp2 = 0;
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while (temp1) {
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not_ok = 0;
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temp2 = __ilog2(temp1);
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debug("checking common caslat = %u\n", temp2);
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/* Check if this CAS latency will work on all DIMMs at tCK. */
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for (i = 0; i < number_of_dimms; i++) {
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if (!dimm_params[i].n_ranks) {
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continue;
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}
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if (dimm_params[i].caslat_X == temp2) {
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if (mclk_ps >= dimm_params[i].tCKmin_X_ps) {
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debug("CL = %u ok on DIMM %u at tCK=%u"
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" ps with its tCKmin_X_ps of %u\n",
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temp2, i, mclk_ps,
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dimm_params[i].tCKmin_X_ps);
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continue;
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} else {
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not_ok++;
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}
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}
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if (dimm_params[i].caslat_X_minus_1 == temp2) {
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unsigned int tCKmin_X_minus_1_ps
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= dimm_params[i].tCKmin_X_minus_1_ps;
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if (mclk_ps >= tCKmin_X_minus_1_ps) {
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debug("CL = %u ok on DIMM %u at "
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"tCK=%u ps with its "
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"tCKmin_X_minus_1_ps of %u\n",
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temp2, i, mclk_ps,
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tCKmin_X_minus_1_ps);
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continue;
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} else {
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not_ok++;
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}
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}
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if (dimm_params[i].caslat_X_minus_2 == temp2) {
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unsigned int tCKmin_X_minus_2_ps
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= dimm_params[i].tCKmin_X_minus_2_ps;
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if (mclk_ps >= tCKmin_X_minus_2_ps) {
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debug("CL = %u ok on DIMM %u at "
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"tCK=%u ps with its "
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"tCKmin_X_minus_2_ps of %u\n",
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temp2, i, mclk_ps,
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tCKmin_X_minus_2_ps);
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continue;
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} else {
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not_ok++;
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}
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}
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}
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if (!not_ok) {
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lowest_good_caslat = temp2;
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}
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temp1 &= ~(1 << temp2);
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}
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debug("lowest common SPD-defined CAS latency = %u\n",
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lowest_good_caslat);
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outpdimm->lowest_common_SPD_caslat = lowest_good_caslat;
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/*
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* Compute a common 'de-rated' CAS latency.
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*
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* The strategy here is to find the *highest* dereated cas latency
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* with the assumption that all of the DIMMs will support a dereated
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* CAS latency higher than or equal to their lowest dereated value.
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*/
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temp1 = 0;
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for (i = 0; i < number_of_dimms; i++) {
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temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
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}
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outpdimm->highest_common_derated_caslat = temp1;
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debug("highest common dereated CAS latency = %u\n", temp1);
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#endif /* #if defined(CONFIG_FSL_DDR3) */
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/* Determine if all DIMMs ECC capable. */
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temp1 = 1;
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for (i = 0; i < number_of_dimms; i++) {
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if (dimm_params[i].n_ranks &&
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!(dimm_params[i].edc_config & EDC_ECC)) {
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temp1 = 0;
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break;
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}
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}
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if (temp1) {
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debug("all DIMMs ECC capable\n");
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} else {
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debug("Warning: not all DIMMs ECC capable, cant enable ECC\n");
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}
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outpdimm->all_DIMMs_ECC_capable = temp1;
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#ifndef CONFIG_FSL_DDR3
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/* FIXME: move to somewhere else to validate. */
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if (mclk_ps > tCKmax_max_ps) {
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printf("Warning: some of the installed DIMMs "
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"can not operate this slowly.\n");
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return 1;
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}
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#endif
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/*
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* Compute additive latency.
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*
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* For DDR1, additive latency should be 0.
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*
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* For DDR2, with ODT enabled, use "a value" less than ACTTORW,
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* which comes from Trcd, and also note that:
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* add_lat + caslat must be >= 4
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*
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* For DDR3, we use the AL=0
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*
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* When to use additive latency for DDR2:
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*
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* I. Because you are using CL=3 and need to do ODT on writes and
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* want functionality.
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* 1. Are you going to use ODT? (Does your board not have
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* additional termination circuitry for DQ, DQS, DQS_,
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* DM, RDQS, RDQS_ for x4/x8 configs?)
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* 2. If so, is your lowest supported CL going to be 3?
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* 3. If so, then you must set AL=1 because
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*
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* WL >= 3 for ODT on writes
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* RL = AL + CL
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* WL = RL - 1
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* ->
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* WL = AL + CL - 1
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* AL + CL - 1 >= 3
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* AL + CL >= 4
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* QED
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*
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* RL >= 3 for ODT on reads
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* RL = AL + CL
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*
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* Since CL aren't usually less than 2, AL=0 is a minimum,
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* so the WL-derived AL should be the -- FIXME?
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*
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* II. Because you are using auto-precharge globally and want to
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* use additive latency (posted CAS) to get more bandwidth.
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* 1. Are you going to use auto-precharge mode globally?
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*
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* Use addtivie latency and compute AL to be 1 cycle less than
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* tRCD, i.e. the READ or WRITE command is in the cycle
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* immediately following the ACTIVATE command..
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*
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* III. Because you feel like it or want to do some sort of
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* degraded-performance experiment.
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* 1. Do you just want to use additive latency because you feel
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* like it?
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*
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* Validation: AL is less than tRCD, and within the other
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* read-to-precharge constraints.
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*/
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additive_latency = 0;
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#if defined(CONFIG_FSL_DDR2)
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if (lowest_good_caslat < 4) {
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additive_latency = (picos_to_mclk(tRCD_ps) > lowest_good_caslat)
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? picos_to_mclk(tRCD_ps) - lowest_good_caslat : 0;
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if (mclk_to_picos(additive_latency) > tRCD_ps) {
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additive_latency = picos_to_mclk(tRCD_ps);
|
|
debug("setting additive_latency to %u because it was "
|
|
" greater than tRCD_ps\n", additive_latency);
|
|
}
|
|
}
|
|
|
|
#elif defined(CONFIG_FSL_DDR3)
|
|
/*
|
|
* The system will not use the global auto-precharge mode.
|
|
* However, it uses the page mode, so we set AL=0
|
|
*/
|
|
additive_latency = 0;
|
|
#endif
|
|
|
|
/*
|
|
* Validate additive latency
|
|
* FIXME: move to somewhere else to validate
|
|
*
|
|
* AL <= tRCD(min)
|
|
*/
|
|
if (mclk_to_picos(additive_latency) > tRCD_ps) {
|
|
printf("Error: invalid additive latency exceeds tRCD(min).\n");
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* RL = CL + AL; RL >= 3 for ODT_RD_CFG to be enabled
|
|
* WL = RL - 1; WL >= 3 for ODT_WL_CFG to be enabled
|
|
* ADD_LAT (the register) must be set to a value less
|
|
* than ACTTORW if WL = 1, then AL must be set to 1
|
|
* RD_TO_PRE (the register) must be set to a minimum
|
|
* tRTP + AL if AL is nonzero
|
|
*/
|
|
|
|
/*
|
|
* Additive latency will be applied only if the memctl option to
|
|
* use it.
|
|
*/
|
|
outpdimm->additive_latency = additive_latency;
|
|
|
|
return 0;
|
|
}
|
|
|