upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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356 lines
8.1 KiB
356 lines
8.1 KiB
/*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <commproc.h>
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#include <mpc8xx.h>
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/* ------------------------------------------------------------------------- */
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static long int dram_size (long int, long int *, long int);
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unsigned long ip860_get_dram_size(void);
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unsigned long ip860_get_clk_freq (void);
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/* ------------------------------------------------------------------------- */
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#define _NOT_USED_ 0xFFFFFFFF
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const uint sdram_table[] = {
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0x1f07fc04, 0xeeaefc04, 0x11adfc04, 0xefbbbc00,
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0x1ff77c47, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1ff77c34, 0xefeabc34, 0x1fb57c35, /* last */
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0x1f07fc04, 0xeeaefc04, 0x10adfc04, 0xf0affc00,
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0xf0affc00, 0xf1affc00, 0xefbbbc00, 0x1ff77c47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0x1f27fc04, 0xeeaebc00, 0x01b93c04, 0x1ff77c47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x1f07fc04, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
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0xf0affc00, 0xe1bbbc04, 0x1ff77c47, /* last */
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_NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPMA RAM)
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*/
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0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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0xfffffc84, 0xfffffc07, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPMA RAM)
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*/
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0x7ffffc07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/* ------------------------------------------------------------------------- */
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int board_early_init_f(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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/* init BCSR chipselect line for ip860_get_clk_freq() and ip860_get_dram_size() */
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memctl->memc_or4 = CFG_OR4;
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memctl->memc_br4 = CFG_BR4;
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*
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* Test ID string (IP860...)
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*/
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int checkboard (void)
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{
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unsigned char *s, *e;
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unsigned char buf[64];
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int i;
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puts ("Board: ");
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i = getenv_r ("serial#", (char *)buf, sizeof (buf));
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s = (i > 0) ? buf : NULL;
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if (!s || strncmp ((char *)s, "IP860", 5)) {
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puts ("### No HW ID - assuming IP860");
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} else {
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for (e = s; *e; ++e) {
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if (*e == ' ')
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break;
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}
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for (; s < e; ++s) {
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putc (*s);
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}
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}
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putc ('\n');
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size;
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ulong refresh_val;
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upmconfig (UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/*
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* Preliminary prescaler for refresh
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*/
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if (ip860_get_clk_freq() == 50000000)
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{
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memctl->memc_mptpr = 0x0400;
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refresh_val = 0xC3000000;
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}
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else
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{
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memctl->memc_mptpr = 0x0200;
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refresh_val = 0x9C000000;
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}
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller banks 2 to the SDRAM address
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*/
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memctl->memc_or2 = CFG_OR2;
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memctl->memc_br2 = CFG_BR2;
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/* IP860 boards have only one bank SDRAM */
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udelay (200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mamr = 0x00804114 | refresh_val;
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memctl->memc_mcr = 0x80004105; /* run precharge pattern from loc 5 */
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udelay(1);
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memctl->memc_mamr = 0x00804118 | refresh_val;
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memctl->memc_mcr = 0x80004130; /* run refresh pattern 8 times */
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udelay (1000);
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/*
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* Check SDRAM Memory Size
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*/
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if (ip860_get_dram_size() == 16)
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size = dram_size (refresh_val | 0x00804114, SDRAM_BASE, SDRAM_MAX_SIZE);
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else
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size = dram_size (refresh_val | 0x00906114, SDRAM_BASE, SDRAM_MAX_SIZE);
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udelay (1000);
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memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
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memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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udelay (10000);
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/*
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* Also, map other memory to correct position
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*/
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#if (defined(CFG_OR1) && defined(CFG_BR1_PRELIM))
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memctl->memc_or1 = CFG_OR1;
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memctl->memc_br1 = CFG_BR1;
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#endif
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#if defined(CFG_OR3) && defined(CFG_BR3)
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memctl->memc_or3 = CFG_OR3;
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memctl->memc_br3 = CFG_BR3;
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#endif
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#if defined(CFG_OR4) && defined(CFG_BR4)
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memctl->memc_or4 = CFG_OR4;
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memctl->memc_br4 = CFG_BR4;
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#endif
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#if defined(CFG_OR5) && defined(CFG_BR5)
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memctl->memc_or5 = CFG_OR5;
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memctl->memc_br5 = CFG_BR5;
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#endif
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#if defined(CFG_OR6) && defined(CFG_BR6)
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memctl->memc_or6 = CFG_OR6;
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memctl->memc_br6 = CFG_BR6;
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#endif
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#if defined(CFG_OR7) && defined(CFG_BR7)
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memctl->memc_or7 = CFG_OR7;
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memctl->memc_br7 = CFG_BR7;
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#endif
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return (size);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mamr_value, long int *base,
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long int maxsize)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_mamr = mamr_value;
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return (get_ram_size(base, maxsize));
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}
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/* ------------------------------------------------------------------------- */
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void reset_phy (void)
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{
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volatile immap_t *immr = (immap_t *) CFG_IMMR;
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ulong mask = PB_ENET_RESET | PB_ENET_JABD;
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ulong reg;
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/* Make sure PHY is not in low-power mode */
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immr->im_cpm.cp_pbpar &= ~(mask); /* GPIO */
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immr->im_cpm.cp_pbodr &= ~(mask); /* active output */
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/* Set JABD low (no JABber Disable),
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* and RESET high (Reset PHY)
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*/
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reg = immr->im_cpm.cp_pbdat;
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reg = (reg & ~PB_ENET_JABD) | PB_ENET_RESET;
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immr->im_cpm.cp_pbdat = reg;
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/* now drive outputs */
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immr->im_cpm.cp_pbdir |= mask; /* output */
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udelay (1000);
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/*
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* Release RESET signal
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*/
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immr->im_cpm.cp_pbdat &= ~(PB_ENET_RESET);
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udelay (1000);
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}
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/* ------------------------------------------------------------------------- */
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unsigned long ip860_get_clk_freq(void)
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{
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volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE;
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ulong temp;
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uchar sysclk;
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if ((bcsr->bd_status & 0x80) == 0x80) /* bd_rev valid ? */
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sysclk = (bcsr->bd_rev & 0x18) >> 3;
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else
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sysclk = 0x00;
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switch (sysclk)
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{
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case 0x00:
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temp = 50000000;
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break;
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case 0x01:
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temp = 80000000;
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break;
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default:
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temp = 50000000;
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break;
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}
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return (temp);
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}
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/* ------------------------------------------------------------------------- */
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unsigned long ip860_get_dram_size(void)
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{
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volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE;
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ulong temp;
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uchar dram_size;
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if ((bcsr->bd_status & 0x80) == 0x80) /* bd_rev valid ? */
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dram_size = (bcsr->bd_rev & 0xE0) >> 5;
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else
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dram_size = 0x00; /* default is 16 MB */
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switch (dram_size)
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{
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case 0x00:
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temp = 16;
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break;
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case 0x01:
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temp = 32;
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break;
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default:
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temp = 16;
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break;
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}
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return (temp);
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}
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/* ------------------------------------------------------------------------- */
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