upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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592 lines
12 KiB
592 lines
12 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017 NXP
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*/
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#include <common.h>
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#include <i2c.h>
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#include <malloc.h>
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#include <errno.h>
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#include <netdev.h>
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#include <fsl_ifc.h>
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#include <fsl_ddr.h>
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#include <fsl_sec.h>
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#include <asm/io.h>
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#include <fdt_support.h>
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#include <linux/libfdt.h>
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#include <fsl-mc/fsl_mc.h>
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#include <environment.h>
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#include <asm/arch-fsl-layerscape/soc.h>
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#include <asm/arch/ppa.h>
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#include <hwconfig.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/soc.h>
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#include "../common/qixis.h"
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#include "ls1088a_qixis.h"
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#include "../common/vid.h"
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#include <fsl_immap.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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#if defined(CONFIG_SYS_I2C_EARLY_INIT) && defined(CONFIG_TARGET_LS1088AQDS)
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i2c_early_init_f();
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#endif
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fsl_lsch3_early_init_f();
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return 0;
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}
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#ifdef CONFIG_FSL_QIXIS
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unsigned long long get_qixis_addr(void)
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{
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unsigned long long addr;
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if (gd->flags & GD_FLG_RELOC)
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addr = QIXIS_BASE_PHYS;
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else
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addr = QIXIS_BASE_PHYS_EARLY;
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/*
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* IFC address under 256MB is mapped to 0x30000000, any address above
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* is mapped to 0x5_10000000 up to 4GB.
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*/
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addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
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return addr;
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}
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#endif
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#if defined(CONFIG_VID)
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int init_func_vid(void)
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{
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if (adjust_vdd(0) < 0)
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printf("core voltage not adjusted\n");
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return 0;
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}
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#endif
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#if !defined(CONFIG_SPL_BUILD)
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int checkboard(void)
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{
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char buf[64];
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u8 sw;
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static const char *const freq[] = {"100", "125", "156.25",
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"100 separate SSCG"};
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int clock;
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#ifdef CONFIG_TARGET_LS1088AQDS
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printf("Board: LS1088A-QDS, ");
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#else
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printf("Board: LS1088A-RDB, ");
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#endif
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sw = QIXIS_READ(arch);
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printf("Board Arch: V%d, ", sw >> 4);
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#ifdef CONFIG_TARGET_LS1088AQDS
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printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
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#else
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printf("Board version: %c, boot from ", (sw & 0xf) + 'A');
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#endif
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memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
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#ifdef CONFIG_SD_BOOT
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puts("SD card\n");
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#endif
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switch (sw) {
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#ifdef CONFIG_TARGET_LS1088AQDS
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case 0:
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case 1:
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case 2:
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case 3:
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case 4:
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case 5:
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case 6:
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case 7:
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printf("vBank: %d\n", sw);
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break;
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case 8:
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puts("PromJet\n");
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break;
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case 15:
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puts("IFCCard\n");
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break;
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case 14:
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#else
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case 0:
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#endif
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puts("QSPI:");
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_QMAP_MASK) >> QIXIS_QMAP_SHIFT;
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if (sw == 0 || sw == 4)
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puts("0\n");
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else if (sw == 1)
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puts("1\n");
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else
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puts("EMU\n");
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break;
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default:
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printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
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break;
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}
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#ifdef CONFIG_TARGET_LS1088AQDS
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printf("FPGA: v%d (%s), build %d",
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(int)QIXIS_READ(scver), qixis_read_tag(buf),
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(int)qixis_read_minor());
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/* the timestamp string contains "\n" at the end */
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printf(" on %s", qixis_read_time(buf));
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#else
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printf("CPLD: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
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#endif
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/*
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* Display the actual SERDES reference clocks as configured by the
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* dip switches on the board. Note that the SWx registers could
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* technically be set to force the reference clocks to match the
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* values that the SERDES expects (or vice versa). For now, however,
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* we just display both values and hope the user notices when they
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* don't match.
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*/
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puts("SERDES1 Reference : ");
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sw = QIXIS_READ(brdcfg[2]);
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clock = (sw >> 6) & 3;
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printf("Clock1 = %sMHz ", freq[clock]);
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clock = (sw >> 4) & 3;
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printf("Clock2 = %sMHz", freq[clock]);
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puts("\nSERDES2 Reference : ");
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clock = (sw >> 2) & 3;
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printf("Clock1 = %sMHz ", freq[clock]);
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clock = (sw >> 0) & 3;
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printf("Clock2 = %sMHz\n", freq[clock]);
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return 0;
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}
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#endif
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bool if_board_diff_clk(void)
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{
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#ifdef CONFIG_TARGET_LS1088AQDS
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u8 diff_conf = QIXIS_READ(brdcfg[11]);
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return diff_conf & 0x40;
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#else
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u8 diff_conf = QIXIS_READ(dutcfg[11]);
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return diff_conf & 0x80;
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#endif
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}
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unsigned long get_board_sys_clk(void)
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{
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
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switch (sysclk_conf & 0x0f) {
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case QIXIS_SYSCLK_83:
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return 83333333;
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case QIXIS_SYSCLK_100:
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return 100000000;
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case QIXIS_SYSCLK_125:
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return 125000000;
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case QIXIS_SYSCLK_133:
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return 133333333;
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case QIXIS_SYSCLK_150:
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return 150000000;
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case QIXIS_SYSCLK_160:
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return 160000000;
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case QIXIS_SYSCLK_166:
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return 166666666;
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}
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return 66666666;
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}
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unsigned long get_board_ddr_clk(void)
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{
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u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
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if (if_board_diff_clk())
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return get_board_sys_clk();
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switch ((ddrclk_conf & 0x30) >> 4) {
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case QIXIS_DDRCLK_100:
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return 100000000;
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case QIXIS_DDRCLK_125:
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return 125000000;
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case QIXIS_DDRCLK_133:
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return 133333333;
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}
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return 66666666;
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}
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int select_i2c_ch_pca9547(u8 ch)
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{
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int ret;
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ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
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if (ret) {
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puts("PCA: failed to select proper channel\n");
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return ret;
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}
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return 0;
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}
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#if !defined(CONFIG_SPL_BUILD)
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void board_retimer_init(void)
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{
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u8 reg;
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/* Retimer is connected to I2C1_CH5 */
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select_i2c_ch_pca9547(I2C_MUX_CH5);
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/* Access to Control/Shared register */
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reg = 0x0;
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i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
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/* Read device revision and ID */
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i2c_read(I2C_RETIMER_ADDR, 1, 1, ®, 1);
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debug("Retimer version id = 0x%x\n", reg);
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/* Enable Broadcast. All writes target all channel register sets */
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reg = 0x0c;
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i2c_write(I2C_RETIMER_ADDR, 0xff, 1, ®, 1);
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/* Reset Channel Registers */
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i2c_read(I2C_RETIMER_ADDR, 0, 1, ®, 1);
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reg |= 0x4;
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i2c_write(I2C_RETIMER_ADDR, 0, 1, ®, 1);
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/* Set data rate as 10.3125 Gbps */
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reg = 0x90;
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i2c_write(I2C_RETIMER_ADDR, 0x60, 1, ®, 1);
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reg = 0xb3;
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i2c_write(I2C_RETIMER_ADDR, 0x61, 1, ®, 1);
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reg = 0x90;
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i2c_write(I2C_RETIMER_ADDR, 0x62, 1, ®, 1);
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reg = 0xb3;
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i2c_write(I2C_RETIMER_ADDR, 0x63, 1, ®, 1);
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reg = 0xcd;
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i2c_write(I2C_RETIMER_ADDR, 0x64, 1, ®, 1);
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/* Select VCO Divider to full rate (000) */
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i2c_read(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
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reg &= 0x0f;
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reg |= 0x70;
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i2c_write(I2C_RETIMER_ADDR, 0x2F, 1, ®, 1);
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#ifdef CONFIG_TARGET_LS1088AQDS
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/* Retimer is connected to I2C1_CH5 */
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select_i2c_ch_pca9547(I2C_MUX_CH5);
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/* Access to Control/Shared register */
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reg = 0x0;
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i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
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/* Read device revision and ID */
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i2c_read(I2C_RETIMER_ADDR2, 1, 1, ®, 1);
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debug("Retimer version id = 0x%x\n", reg);
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/* Enable Broadcast. All writes target all channel register sets */
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reg = 0x0c;
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i2c_write(I2C_RETIMER_ADDR2, 0xff, 1, ®, 1);
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/* Reset Channel Registers */
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i2c_read(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
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reg |= 0x4;
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i2c_write(I2C_RETIMER_ADDR2, 0, 1, ®, 1);
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/* Set data rate as 10.3125 Gbps */
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reg = 0x90;
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i2c_write(I2C_RETIMER_ADDR2, 0x60, 1, ®, 1);
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reg = 0xb3;
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i2c_write(I2C_RETIMER_ADDR2, 0x61, 1, ®, 1);
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reg = 0x90;
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i2c_write(I2C_RETIMER_ADDR2, 0x62, 1, ®, 1);
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reg = 0xb3;
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i2c_write(I2C_RETIMER_ADDR2, 0x63, 1, ®, 1);
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reg = 0xcd;
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i2c_write(I2C_RETIMER_ADDR2, 0x64, 1, ®, 1);
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/* Select VCO Divider to full rate (000) */
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i2c_read(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
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reg &= 0x0f;
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reg |= 0x70;
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i2c_write(I2C_RETIMER_ADDR2, 0x2F, 1, ®, 1);
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#endif
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/*return the default channel*/
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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}
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#ifdef CONFIG_MISC_INIT_R
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int misc_init_r(void)
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{
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#ifdef CONFIG_TARGET_LS1088ARDB
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u8 brdcfg5;
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if (hwconfig("esdhc-force-sd")) {
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brdcfg5 = QIXIS_READ(brdcfg[5]);
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brdcfg5 &= ~BRDCFG5_SPISDHC_MASK;
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brdcfg5 |= BRDCFG5_FORCE_SD;
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QIXIS_WRITE(brdcfg[5], brdcfg5);
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}
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#endif
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return 0;
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}
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#endif
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#endif
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int i2c_multiplexer_select_vid_channel(u8 channel)
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{
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return select_i2c_ch_pca9547(channel);
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}
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#ifdef CONFIG_TARGET_LS1088AQDS
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/* read the current value(SVDD) of the LTM Regulator Voltage */
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int get_serdes_volt(void)
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{
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int ret, vcode = 0;
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u8 chan = PWM_CHANNEL0;
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/* Select the PAGE 0 using PMBus commands PAGE for VDD */
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ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
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PMBUS_CMD_PAGE, 1, &chan, 1);
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if (ret) {
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printf("VID: failed to select VDD Page 0\n");
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return ret;
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}
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/* Read the output voltage using PMBus command READ_VOUT */
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ret = i2c_read(I2C_SVDD_MONITOR_ADDR,
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PMBUS_CMD_READ_VOUT, 1, (void *)&vcode, 2);
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if (ret) {
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printf("VID: failed to read the volatge\n");
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return ret;
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}
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return vcode;
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}
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int set_serdes_volt(int svdd)
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{
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int ret, vdd_last;
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u8 buff[5] = {0x04, PWM_CHANNEL0, PMBUS_CMD_VOUT_COMMAND,
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svdd & 0xFF, (svdd & 0xFF00) >> 8};
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/* Write the desired voltage code to the SVDD regulator */
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ret = i2c_write(I2C_SVDD_MONITOR_ADDR,
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PMBUS_CMD_PAGE_PLUS_WRITE, 1, (void *)&buff, 5);
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if (ret) {
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printf("VID: I2C failed to write to the volatge regulator\n");
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return -1;
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}
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/* Wait for the volatge to get to the desired value */
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do {
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vdd_last = get_serdes_volt();
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if (vdd_last < 0) {
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printf("VID: Couldn't read sensor abort VID adjust\n");
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return -1;
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}
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} while (vdd_last != svdd);
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return 1;
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}
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#else
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int get_serdes_volt(void)
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{
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return 0;
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}
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int set_serdes_volt(int svdd)
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{
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int ret;
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u8 brdcfg4;
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printf("SVDD changing of RDB\n");
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/* Read the BRDCFG54 via CLPD */
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ret = i2c_read(CONFIG_SYS_I2C_FPGA_ADDR,
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QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
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if (ret) {
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printf("VID: I2C failed to read the CPLD BRDCFG4\n");
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return -1;
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}
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brdcfg4 = brdcfg4 | 0x08;
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/* Write to the BRDCFG4 */
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ret = i2c_write(CONFIG_SYS_I2C_FPGA_ADDR,
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QIXIS_BRDCFG4_OFFSET, 1, (void *)&brdcfg4, 1);
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if (ret) {
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debug("VID: I2C failed to set the SVDD CPLD BRDCFG4\n");
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return -1;
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}
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/* Wait for the volatge to get to the desired value */
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udelay(10000);
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return 1;
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}
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#endif
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/* this function disables the SERDES, changes the SVDD Voltage and enables it*/
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int board_adjust_vdd(int vdd)
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{
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int ret = 0;
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debug("%s: vdd = %d\n", __func__, vdd);
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/* Special settings to be performed when voltage is 900mV */
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if (vdd == 900) {
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ret = setup_serdes_volt(vdd);
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if (ret < 0) {
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ret = -1;
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goto exit;
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}
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}
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exit:
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return ret;
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}
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#if !defined(CONFIG_SPL_BUILD)
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int board_init(void)
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{
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init_final_memctl_regs();
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#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
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u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
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#endif
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select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
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board_retimer_init();
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#ifdef CONFIG_ENV_IS_NOWHERE
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gd->env_addr = (ulong)&default_environment[0];
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#endif
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#if defined(CONFIG_TARGET_LS1088ARDB) && defined(CONFIG_FSL_MC_ENET)
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/* invert AQR105 IRQ pins polarity */
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out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR105_IRQ_MASK);
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#endif
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#ifdef CONFIG_FSL_CAAM
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sec_init();
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#endif
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#ifdef CONFIG_FSL_LS_PPA
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ppa_init();
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#endif
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return 0;
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}
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void detail_board_ddr_info(void)
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{
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puts("\nDDR ");
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print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
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print_ddr_info(0);
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}
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#if defined(CONFIG_ARCH_MISC_INIT)
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int arch_misc_init(void)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_FSL_MC_ENET
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void fdt_fixup_board_enet(void *fdt)
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{
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int offset;
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|
|
offset = fdt_path_offset(fdt, "/fsl-mc");
|
|
|
|
if (offset < 0)
|
|
offset = fdt_path_offset(fdt, "/fsl,dprc@0");
|
|
|
|
if (offset < 0) {
|
|
printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
|
|
__func__, offset);
|
|
return;
|
|
}
|
|
|
|
if ((get_mc_boot_status() == 0) && (get_dpl_apply_status() == 0))
|
|
fdt_status_okay(fdt, offset);
|
|
else
|
|
fdt_status_fail(fdt, offset);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_OF_BOARD_SETUP
|
|
void fsl_fdt_fixup_flash(void *fdt)
|
|
{
|
|
int offset;
|
|
|
|
/*
|
|
* IFC-NOR and QSPI are muxed on SoC.
|
|
* So disable IFC node in dts if QSPI is enabled or
|
|
* disable QSPI node in dts in case QSPI is not enabled.
|
|
*/
|
|
|
|
#ifdef CONFIG_FSL_QSPI
|
|
offset = fdt_path_offset(fdt, "/soc/ifc/nor");
|
|
|
|
if (offset < 0)
|
|
offset = fdt_path_offset(fdt, "/ifc/nor");
|
|
#else
|
|
offset = fdt_path_offset(fdt, "/soc/quadspi");
|
|
|
|
if (offset < 0)
|
|
offset = fdt_path_offset(fdt, "/quadspi");
|
|
#endif
|
|
if (offset < 0)
|
|
return;
|
|
|
|
fdt_status_disabled(fdt, offset);
|
|
}
|
|
|
|
int ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
int err, i;
|
|
u64 base[CONFIG_NR_DRAM_BANKS];
|
|
u64 size[CONFIG_NR_DRAM_BANKS];
|
|
|
|
ft_cpu_setup(blob, bd);
|
|
|
|
/* fixup DT for the two GPP DDR banks */
|
|
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
|
|
base[i] = gd->bd->bi_dram[i].start;
|
|
size[i] = gd->bd->bi_dram[i].size;
|
|
}
|
|
|
|
#ifdef CONFIG_RESV_RAM
|
|
/* reduce size if reserved memory is within this bank */
|
|
if (gd->arch.resv_ram >= base[0] &&
|
|
gd->arch.resv_ram < base[0] + size[0])
|
|
size[0] = gd->arch.resv_ram - base[0];
|
|
else if (gd->arch.resv_ram >= base[1] &&
|
|
gd->arch.resv_ram < base[1] + size[1])
|
|
size[1] = gd->arch.resv_ram - base[1];
|
|
#endif
|
|
|
|
fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS);
|
|
|
|
fdt_fsl_mc_fixup_iommu_map_entry(blob);
|
|
|
|
fsl_fdt_fixup_flash(blob);
|
|
|
|
#ifdef CONFIG_FSL_MC_ENET
|
|
fdt_fixup_board_enet(blob);
|
|
err = fsl_mc_ldpaa_exit(bd);
|
|
if (err)
|
|
return err;
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
#endif /* defined(CONFIG_SPL_BUILD) */
|
|
|