upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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639 lines
13 KiB
639 lines
13 KiB
/*
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* Copyright (C) 2010 Samsung Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/clk.h>
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/* exynos4: return pll clock frequency */
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static unsigned long exynos4_get_pll_clk(int pllreg)
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{
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struct exynos4_clock *clk =
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(struct exynos4_clock *)samsung_get_base_clock();
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unsigned long r, m, p, s, k = 0, mask, fout;
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unsigned int freq;
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switch (pllreg) {
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case APLL:
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r = readl(&clk->apll_con0);
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break;
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case MPLL:
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r = readl(&clk->mpll_con0);
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break;
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case EPLL:
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r = readl(&clk->epll_con0);
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k = readl(&clk->epll_con1);
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break;
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case VPLL:
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r = readl(&clk->vpll_con0);
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k = readl(&clk->vpll_con1);
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break;
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default:
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printf("Unsupported PLL (%d)\n", pllreg);
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return 0;
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}
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/*
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* APLL_CON: MIDV [25:16]
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* MPLL_CON: MIDV [25:16]
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* EPLL_CON: MIDV [24:16]
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* VPLL_CON: MIDV [24:16]
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*/
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if (pllreg == APLL || pllreg == MPLL)
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mask = 0x3ff;
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else
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mask = 0x1ff;
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m = (r >> 16) & mask;
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/* PDIV [13:8] */
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p = (r >> 8) & 0x3f;
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/* SDIV [2:0] */
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s = r & 0x7;
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freq = CONFIG_SYS_CLK_FREQ;
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if (pllreg == EPLL) {
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k = k & 0xffff;
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/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
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fout = (m + k / 65536) * (freq / (p * (1 << s)));
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} else if (pllreg == VPLL) {
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k = k & 0xfff;
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/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
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fout = (m + k / 1024) * (freq / (p * (1 << s)));
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} else {
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if (s < 1)
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s = 1;
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/* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
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fout = m * (freq / (p * (1 << (s - 1))));
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}
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return fout;
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}
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/* exynos5: return pll clock frequency */
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static unsigned long exynos5_get_pll_clk(int pllreg)
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{
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struct exynos5_clock *clk =
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(struct exynos5_clock *)samsung_get_base_clock();
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unsigned long r, m, p, s, k = 0, mask, fout;
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unsigned int freq;
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switch (pllreg) {
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case APLL:
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r = readl(&clk->apll_con0);
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break;
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case MPLL:
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r = readl(&clk->mpll_con0);
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break;
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case EPLL:
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r = readl(&clk->epll_con0);
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k = readl(&clk->epll_con1);
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break;
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case VPLL:
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r = readl(&clk->vpll_con0);
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k = readl(&clk->vpll_con1);
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break;
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default:
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printf("Unsupported PLL (%d)\n", pllreg);
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return 0;
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}
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/*
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* APLL_CON: MIDV [25:16]
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* MPLL_CON: MIDV [25:16]
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* EPLL_CON: MIDV [24:16]
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* VPLL_CON: MIDV [24:16]
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*/
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if (pllreg == APLL || pllreg == MPLL)
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mask = 0x3ff;
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else
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mask = 0x1ff;
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m = (r >> 16) & mask;
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/* PDIV [13:8] */
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p = (r >> 8) & 0x3f;
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/* SDIV [2:0] */
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s = r & 0x7;
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freq = CONFIG_SYS_CLK_FREQ;
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if (pllreg == EPLL) {
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k = k & 0xffff;
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/* FOUT = (MDIV + K / 65536) * FIN / (PDIV * 2^SDIV) */
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fout = (m + k / 65536) * (freq / (p * (1 << s)));
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} else if (pllreg == VPLL) {
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k = k & 0xfff;
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/* FOUT = (MDIV + K / 1024) * FIN / (PDIV * 2^SDIV) */
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fout = (m + k / 1024) * (freq / (p * (1 << s)));
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} else {
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if (s < 1)
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s = 1;
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/* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
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fout = m * (freq / (p * (1 << (s - 1))));
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}
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return fout;
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}
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/* exynos4: return ARM clock frequency */
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static unsigned long exynos4_get_arm_clk(void)
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{
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struct exynos4_clock *clk =
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(struct exynos4_clock *)samsung_get_base_clock();
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unsigned long div;
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unsigned long armclk;
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unsigned int core_ratio;
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unsigned int core2_ratio;
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div = readl(&clk->div_cpu0);
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/* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */
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core_ratio = (div >> 0) & 0x7;
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core2_ratio = (div >> 28) & 0x7;
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armclk = get_pll_clk(APLL) / (core_ratio + 1);
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armclk /= (core2_ratio + 1);
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return armclk;
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}
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/* exynos5: return ARM clock frequency */
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static unsigned long exynos5_get_arm_clk(void)
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{
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struct exynos5_clock *clk =
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(struct exynos5_clock *)samsung_get_base_clock();
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unsigned long div;
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unsigned long armclk;
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unsigned int arm_ratio;
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unsigned int arm2_ratio;
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div = readl(&clk->div_cpu0);
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/* ARM_RATIO: [2:0], ARM2_RATIO: [30:28] */
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arm_ratio = (div >> 0) & 0x7;
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arm2_ratio = (div >> 28) & 0x7;
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armclk = get_pll_clk(APLL) / (arm_ratio + 1);
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armclk /= (arm2_ratio + 1);
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return armclk;
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}
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/* exynos4: return pwm clock frequency */
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static unsigned long exynos4_get_pwm_clk(void)
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{
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struct exynos4_clock *clk =
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(struct exynos4_clock *)samsung_get_base_clock();
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unsigned long pclk, sclk;
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unsigned int sel;
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unsigned int ratio;
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if (s5p_get_cpu_rev() == 0) {
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/*
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* CLK_SRC_PERIL0
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* PWM_SEL [27:24]
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*/
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sel = readl(&clk->src_peril0);
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sel = (sel >> 24) & 0xf;
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if (sel == 0x6)
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sclk = get_pll_clk(MPLL);
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else if (sel == 0x7)
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sclk = get_pll_clk(EPLL);
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else if (sel == 0x8)
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sclk = get_pll_clk(VPLL);
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else
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return 0;
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/*
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* CLK_DIV_PERIL3
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* PWM_RATIO [3:0]
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*/
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ratio = readl(&clk->div_peril3);
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ratio = ratio & 0xf;
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} else if (s5p_get_cpu_rev() == 1) {
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sclk = get_pll_clk(MPLL);
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ratio = 8;
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} else
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return 0;
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pclk = sclk / (ratio + 1);
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return pclk;
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}
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/* exynos5: return pwm clock frequency */
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static unsigned long exynos5_get_pwm_clk(void)
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{
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struct exynos5_clock *clk =
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(struct exynos5_clock *)samsung_get_base_clock();
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unsigned long pclk, sclk;
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unsigned int ratio;
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/*
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* CLK_DIV_PERIC3
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* PWM_RATIO [3:0]
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*/
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ratio = readl(&clk->div_peric3);
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ratio = ratio & 0xf;
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sclk = get_pll_clk(MPLL);
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pclk = sclk / (ratio + 1);
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return pclk;
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}
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/* exynos4: return uart clock frequency */
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static unsigned long exynos4_get_uart_clk(int dev_index)
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{
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struct exynos4_clock *clk =
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(struct exynos4_clock *)samsung_get_base_clock();
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unsigned long uclk, sclk;
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unsigned int sel;
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unsigned int ratio;
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/*
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* CLK_SRC_PERIL0
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* UART0_SEL [3:0]
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* UART1_SEL [7:4]
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* UART2_SEL [8:11]
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* UART3_SEL [12:15]
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* UART4_SEL [16:19]
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* UART5_SEL [23:20]
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*/
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sel = readl(&clk->src_peril0);
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sel = (sel >> (dev_index << 2)) & 0xf;
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if (sel == 0x6)
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sclk = get_pll_clk(MPLL);
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else if (sel == 0x7)
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sclk = get_pll_clk(EPLL);
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else if (sel == 0x8)
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sclk = get_pll_clk(VPLL);
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else
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return 0;
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/*
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* CLK_DIV_PERIL0
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* UART0_RATIO [3:0]
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* UART1_RATIO [7:4]
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* UART2_RATIO [8:11]
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* UART3_RATIO [12:15]
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* UART4_RATIO [16:19]
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* UART5_RATIO [23:20]
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*/
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ratio = readl(&clk->div_peril0);
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ratio = (ratio >> (dev_index << 2)) & 0xf;
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uclk = sclk / (ratio + 1);
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return uclk;
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}
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/* exynos5: return uart clock frequency */
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static unsigned long exynos5_get_uart_clk(int dev_index)
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{
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struct exynos5_clock *clk =
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(struct exynos5_clock *)samsung_get_base_clock();
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unsigned long uclk, sclk;
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unsigned int sel;
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unsigned int ratio;
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/*
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* CLK_SRC_PERIC0
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* UART0_SEL [3:0]
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* UART1_SEL [7:4]
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* UART2_SEL [8:11]
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* UART3_SEL [12:15]
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* UART4_SEL [16:19]
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* UART5_SEL [23:20]
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*/
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sel = readl(&clk->src_peric0);
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sel = (sel >> (dev_index << 2)) & 0xf;
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if (sel == 0x6)
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sclk = get_pll_clk(MPLL);
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else if (sel == 0x7)
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sclk = get_pll_clk(EPLL);
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else if (sel == 0x8)
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sclk = get_pll_clk(VPLL);
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else
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return 0;
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/*
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* CLK_DIV_PERIC0
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* UART0_RATIO [3:0]
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* UART1_RATIO [7:4]
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* UART2_RATIO [8:11]
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* UART3_RATIO [12:15]
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* UART4_RATIO [16:19]
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* UART5_RATIO [23:20]
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*/
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ratio = readl(&clk->div_peric0);
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ratio = (ratio >> (dev_index << 2)) & 0xf;
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uclk = sclk / (ratio + 1);
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return uclk;
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}
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/* exynos4: set the mmc clock */
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static void exynos4_set_mmc_clk(int dev_index, unsigned int div)
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{
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struct exynos4_clock *clk =
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(struct exynos4_clock *)samsung_get_base_clock();
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unsigned int addr;
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unsigned int val;
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/*
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* CLK_DIV_FSYS1
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* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
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* CLK_DIV_FSYS2
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* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
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*/
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if (dev_index < 2) {
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addr = (unsigned int)&clk->div_fsys1;
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} else {
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addr = (unsigned int)&clk->div_fsys2;
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dev_index -= 2;
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}
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val = readl(addr);
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val &= ~(0xff << ((dev_index << 4) + 8));
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val |= (div & 0xff) << ((dev_index << 4) + 8);
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writel(val, addr);
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}
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/* exynos5: set the mmc clock */
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static void exynos5_set_mmc_clk(int dev_index, unsigned int div)
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{
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struct exynos5_clock *clk =
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(struct exynos5_clock *)samsung_get_base_clock();
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unsigned int addr;
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unsigned int val;
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/*
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* CLK_DIV_FSYS1
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* MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24]
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* CLK_DIV_FSYS2
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* MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24]
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*/
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if (dev_index < 2) {
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addr = (unsigned int)&clk->div_fsys1;
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} else {
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addr = (unsigned int)&clk->div_fsys2;
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dev_index -= 2;
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}
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val = readl(addr);
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val &= ~(0xff << ((dev_index << 4) + 8));
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val |= (div & 0xff) << ((dev_index << 4) + 8);
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writel(val, addr);
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}
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/* get_lcd_clk: return lcd clock frequency */
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static unsigned long exynos4_get_lcd_clk(void)
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{
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struct exynos4_clock *clk =
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(struct exynos4_clock *)samsung_get_base_clock();
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unsigned long pclk, sclk;
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unsigned int sel;
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unsigned int ratio;
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/*
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* CLK_SRC_LCD0
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* FIMD0_SEL [3:0]
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*/
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sel = readl(&clk->src_lcd0);
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sel = sel & 0xf;
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/*
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* 0x6: SCLK_MPLL
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* 0x7: SCLK_EPLL
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* 0x8: SCLK_VPLL
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*/
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if (sel == 0x6)
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sclk = get_pll_clk(MPLL);
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else if (sel == 0x7)
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sclk = get_pll_clk(EPLL);
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else if (sel == 0x8)
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sclk = get_pll_clk(VPLL);
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else
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return 0;
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/*
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* CLK_DIV_LCD0
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* FIMD0_RATIO [3:0]
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*/
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ratio = readl(&clk->div_lcd0);
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ratio = ratio & 0xf;
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pclk = sclk / (ratio + 1);
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return pclk;
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}
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void exynos4_set_lcd_clk(void)
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{
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struct exynos4_clock *clk =
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(struct exynos4_clock *)samsung_get_base_clock();
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unsigned int cfg = 0;
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/*
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* CLK_GATE_BLOCK
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* CLK_CAM [0]
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* CLK_TV [1]
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* CLK_MFC [2]
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* CLK_G3D [3]
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* CLK_LCD0 [4]
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* CLK_LCD1 [5]
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* CLK_GPS [7]
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*/
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cfg = readl(&clk->gate_block);
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cfg |= 1 << 4;
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writel(cfg, &clk->gate_block);
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/*
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* CLK_SRC_LCD0
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* FIMD0_SEL [3:0]
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* MDNIE0_SEL [7:4]
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* MDNIE_PWM0_SEL [8:11]
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* MIPI0_SEL [12:15]
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* set lcd0 src clock 0x6: SCLK_MPLL
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*/
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cfg = readl(&clk->src_lcd0);
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cfg &= ~(0xf);
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cfg |= 0x6;
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writel(cfg, &clk->src_lcd0);
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/*
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* CLK_GATE_IP_LCD0
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* CLK_FIMD0 [0]
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* CLK_MIE0 [1]
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* CLK_MDNIE0 [2]
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* CLK_DSIM0 [3]
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* CLK_SMMUFIMD0 [4]
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* CLK_PPMULCD0 [5]
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* Gating all clocks for FIMD0
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*/
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cfg = readl(&clk->gate_ip_lcd0);
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cfg |= 1 << 0;
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writel(cfg, &clk->gate_ip_lcd0);
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/*
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* CLK_DIV_LCD0
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* FIMD0_RATIO [3:0]
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* MDNIE0_RATIO [7:4]
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* MDNIE_PWM0_RATIO [11:8]
|
|
* MDNIE_PWM_PRE_RATIO [15:12]
|
|
* MIPI0_RATIO [19:16]
|
|
* MIPI0_PRE_RATIO [23:20]
|
|
* set fimd ratio
|
|
*/
|
|
cfg &= ~(0xf);
|
|
cfg |= 0x1;
|
|
writel(cfg, &clk->div_lcd0);
|
|
}
|
|
|
|
void exynos4_set_mipi_clk(void)
|
|
{
|
|
struct exynos4_clock *clk =
|
|
(struct exynos4_clock *)samsung_get_base_clock();
|
|
unsigned int cfg = 0;
|
|
|
|
/*
|
|
* CLK_SRC_LCD0
|
|
* FIMD0_SEL [3:0]
|
|
* MDNIE0_SEL [7:4]
|
|
* MDNIE_PWM0_SEL [8:11]
|
|
* MIPI0_SEL [12:15]
|
|
* set mipi0 src clock 0x6: SCLK_MPLL
|
|
*/
|
|
cfg = readl(&clk->src_lcd0);
|
|
cfg &= ~(0xf << 12);
|
|
cfg |= (0x6 << 12);
|
|
writel(cfg, &clk->src_lcd0);
|
|
|
|
/*
|
|
* CLK_SRC_MASK_LCD0
|
|
* FIMD0_MASK [0]
|
|
* MDNIE0_MASK [4]
|
|
* MDNIE_PWM0_MASK [8]
|
|
* MIPI0_MASK [12]
|
|
* set src mask mipi0 0x1: Unmask
|
|
*/
|
|
cfg = readl(&clk->src_mask_lcd0);
|
|
cfg |= (0x1 << 12);
|
|
writel(cfg, &clk->src_mask_lcd0);
|
|
|
|
/*
|
|
* CLK_GATE_IP_LCD0
|
|
* CLK_FIMD0 [0]
|
|
* CLK_MIE0 [1]
|
|
* CLK_MDNIE0 [2]
|
|
* CLK_DSIM0 [3]
|
|
* CLK_SMMUFIMD0 [4]
|
|
* CLK_PPMULCD0 [5]
|
|
* Gating all clocks for MIPI0
|
|
*/
|
|
cfg = readl(&clk->gate_ip_lcd0);
|
|
cfg |= 1 << 3;
|
|
writel(cfg, &clk->gate_ip_lcd0);
|
|
|
|
/*
|
|
* CLK_DIV_LCD0
|
|
* FIMD0_RATIO [3:0]
|
|
* MDNIE0_RATIO [7:4]
|
|
* MDNIE_PWM0_RATIO [11:8]
|
|
* MDNIE_PWM_PRE_RATIO [15:12]
|
|
* MIPI0_RATIO [19:16]
|
|
* MIPI0_PRE_RATIO [23:20]
|
|
* set mipi ratio
|
|
*/
|
|
cfg &= ~(0xf << 16);
|
|
cfg |= (0x1 << 16);
|
|
writel(cfg, &clk->div_lcd0);
|
|
}
|
|
|
|
unsigned long get_pll_clk(int pllreg)
|
|
{
|
|
if (cpu_is_exynos5())
|
|
return exynos5_get_pll_clk(pllreg);
|
|
else
|
|
return exynos4_get_pll_clk(pllreg);
|
|
}
|
|
|
|
unsigned long get_arm_clk(void)
|
|
{
|
|
if (cpu_is_exynos5())
|
|
return exynos5_get_arm_clk();
|
|
else
|
|
return exynos4_get_arm_clk();
|
|
}
|
|
|
|
unsigned long get_pwm_clk(void)
|
|
{
|
|
if (cpu_is_exynos5())
|
|
return exynos5_get_pwm_clk();
|
|
else
|
|
return exynos4_get_pwm_clk();
|
|
}
|
|
|
|
unsigned long get_uart_clk(int dev_index)
|
|
{
|
|
if (cpu_is_exynos5())
|
|
return exynos5_get_uart_clk(dev_index);
|
|
else
|
|
return exynos4_get_uart_clk(dev_index);
|
|
}
|
|
|
|
void set_mmc_clk(int dev_index, unsigned int div)
|
|
{
|
|
if (cpu_is_exynos5())
|
|
exynos5_set_mmc_clk(dev_index, div);
|
|
else
|
|
exynos4_set_mmc_clk(dev_index, div);
|
|
}
|
|
|
|
unsigned long get_lcd_clk(void)
|
|
{
|
|
if (cpu_is_exynos4())
|
|
return exynos4_get_lcd_clk();
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
void set_lcd_clk(void)
|
|
{
|
|
if (cpu_is_exynos4())
|
|
exynos4_set_lcd_clk();
|
|
}
|
|
|
|
void set_mipi_clk(void)
|
|
{
|
|
if (cpu_is_exynos4())
|
|
exynos4_set_mipi_clk();
|
|
}
|
|
|