upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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144 lines
3.8 KiB
144 lines
3.8 KiB
/*
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* Copyright (C) 2005-2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#ifdef CFG_HSDRAMC
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#include <asm/io.h>
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#include <asm/sdram.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/memory-map.h>
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#include "hsdramc1.h"
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unsigned long sdram_init(const struct sdram_info *info)
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{
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unsigned long *sdram = (unsigned long *)uncached(info->phys_addr);
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unsigned long sdram_size;
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unsigned long tmp;
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unsigned long bus_hz;
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unsigned int i;
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if (!info->refresh_period)
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panic("ERROR: SDRAM refresh period == 0. "
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"Please update the board code\n");
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tmp = (HSDRAMC1_BF(NC, info->col_bits - 8)
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| HSDRAMC1_BF(NR, info->row_bits - 11)
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| HSDRAMC1_BF(NB, info->bank_bits - 1)
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| HSDRAMC1_BF(CAS, info->cas)
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| HSDRAMC1_BF(TWR, info->twr)
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| HSDRAMC1_BF(TRC, info->trc)
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| HSDRAMC1_BF(TRP, info->trp)
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| HSDRAMC1_BF(TRCD, info->trcd)
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| HSDRAMC1_BF(TRAS, info->tras)
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| HSDRAMC1_BF(TXSR, info->txsr));
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#ifdef CFG_SDRAM_16BIT
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tmp |= HSDRAMC1_BIT(DBW);
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sdram_size = 1 << (info->row_bits + info->col_bits
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+ info->bank_bits + 1);
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#else
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sdram_size = 1 << (info->row_bits + info->col_bits
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+ info->bank_bits + 2);
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#endif
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hsdramc1_writel(CR, tmp);
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/*
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* Initialization sequence for SDRAM, from the data sheet:
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*
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* 1. A minimum pause of 200 us is provided to precede any
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* signal toggle.
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*/
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udelay(200);
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/*
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* 2. A Precharge All command is issued to the SDRAM
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*/
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hsdramc1_writel(MR, HSDRAMC1_MODE_BANKS_PRECHARGE);
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hsdramc1_readl(MR);
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writel(0, sdram);
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/*
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* 3. Eight auto-refresh (CBR) cycles are provided
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*/
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hsdramc1_writel(MR, HSDRAMC1_MODE_AUTO_REFRESH);
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hsdramc1_readl(MR);
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for (i = 0; i < 8; i++)
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writel(0, sdram);
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/*
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* 4. A mode register set (MRS) cycle is issued to program
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* SDRAM parameters, in particular CAS latency and burst
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* length.
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*
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* CAS from info struct, burst length 1, serial burst type
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*/
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hsdramc1_writel(MR, HSDRAMC1_MODE_LOAD_MODE);
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hsdramc1_readl(MR);
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writel(0, sdram + (info->cas << 4));
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/*
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* 5. A Normal Mode command is provided, 3 clocks after tMRD
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* is met.
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*
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* From the timing diagram, it looks like tMRD is 3
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* cycles...try a dummy read from the peripheral bus.
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*/
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hsdramc1_readl(MR);
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hsdramc1_writel(MR, HSDRAMC1_MODE_NORMAL);
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hsdramc1_readl(MR);
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writel(0, sdram);
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/*
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* 6. Write refresh rate into SDRAMC refresh timer count
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* register (refresh rate = timing between refresh cycles).
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*
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* 15.6 us is a typical value for a burst of length one
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*/
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bus_hz = get_sdram_clk_rate();
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hsdramc1_writel(TR, info->refresh_period);
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printf("SDRAM: %u MB at address 0x%08lx\n",
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sdram_size >> 20, info->phys_addr);
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printf("Testing SDRAM...");
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for (i = 0; i < sdram_size / 4; i++)
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sdram[i] = i;
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for (i = 0; i < sdram_size / 4; i++) {
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tmp = sdram[i];
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if (tmp != i) {
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printf("FAILED at address 0x%08lx\n",
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info->phys_addr + i * 4);
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printf("SDRAM: read 0x%lx, expected 0x%lx\n", tmp, i);
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return 0;
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}
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}
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puts("OK\n");
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return sdram_size;
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}
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#endif /* CFG_HSDRAMC */
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