upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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109 lines
4.6 KiB
109 lines
4.6 KiB
/*
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* Misc Core Masks
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*/
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#ifndef __BFIN_PERIPHERAL_CORE__
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#define __BFIN_PERIPHERAL_CORE__
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/*
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* EVT registers (ILAT, IMASK, and IPEND).
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*/
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#define EVT_EMU_P 0 /* Emulator interrupt bit position */
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#define EVT_RST_P 1 /* Reset interrupt bit position */
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#define EVT_NMI_P 2 /* Non Maskable interrupt bit position */
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#define EVT_EVX_P 3 /* Exception bit position */
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#define EVT_IRPTEN_P 4 /* Global interrupt enable bit position */
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#define EVT_IVHW_P 5 /* Hardware Error interrupt bit position */
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#define EVT_IVTMR_P 6 /* Timer interrupt bit position */
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#define EVT_IVG7_P 7 /* IVG7 interrupt bit position */
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#define EVT_IVG8_P 8 /* IVG8 interrupt bit position */
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#define EVT_IVG9_P 9 /* IVG9 interrupt bit position */
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#define EVT_IVG10_P 10 /* IVG10 interrupt bit position */
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#define EVT_IVG11_P 11 /* IVG11 interrupt bit position */
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#define EVT_IVG12_P 12 /* IVG12 interrupt bit position */
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#define EVT_IVG13_P 13 /* IVG13 interrupt bit position */
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#define EVT_IVG14_P 14 /* IVG14 interrupt bit position */
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#define EVT_IVG15_P 15 /* IVG15 interrupt bit position */
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#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
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#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
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#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
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#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
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#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
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#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
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#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
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#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
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#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
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#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
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#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
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#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
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#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
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#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
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#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
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#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
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/*
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* SEQSTAT register
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*/
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#define EXCAUSE_P 0 /* Last exception cause bit positions */
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#define EXCAUSE0_P 0 /* Last exception cause bit 0 */
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#define EXCAUSE1_P 1 /* Last exception cause bit 1 */
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#define EXCAUSE2_P 2 /* Last exception cause bit 2 */
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#define EXCAUSE3_P 3 /* Last exception cause bit 3 */
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#define EXCAUSE4_P 4 /* Last exception cause bit 4 */
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#define EXCAUSE5_P 5 /* Last exception cause bit 5 */
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#define IDLE_REQ_P 12 /* Pending idle mode request, set by IDLE instruction */
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#define SFTRESET_P 13 /* Indicates whether the last reset was a software reset (=1) */
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#define HWERRCAUSE_P 14 /* Last hw error cause bit positions */
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#define HWERRCAUSE0_P 14 /* Last hw error cause bit 0 */
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#define HWERRCAUSE1_P 15 /* Last hw error cause bit 1 */
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#define HWERRCAUSE2_P 16 /* Last hw error cause bit 2 */
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#define HWERRCAUSE3_P 17 /* Last hw error cause bit 3 */
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#define HWERRCAUSE4_P 18 /* Last hw error cause bit 4 */
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#define HWERRCAUSE5_P 19 /* Last hw error cause bit 5 */
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#define HWERRCAUSE6_P 20 /* Last hw error cause bit 6 */
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#define HWERRCAUSE7_P 21 /* Last hw error cause bit 7 */
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#define EXCAUSE \
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( MK_BMSK_(EXCAUSE0_P) | \
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MK_BMSK_(EXCAUSE1_P) | \
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MK_BMSK_(EXCAUSE2_P) | \
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MK_BMSK_(EXCAUSE3_P) | \
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MK_BMSK_(EXCAUSE4_P) | \
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MK_BMSK_(EXCAUSE5_P) )
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#define SFTRESET \
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( MK_BMSK_(SFTRESET_P) )
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#define HWERRCAUSE \
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( MK_BMSK_(HWERRCAUSE0_P) | \
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MK_BMSK_(HWERRCAUSE1_P) | \
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MK_BMSK_(HWERRCAUSE2_P) | \
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MK_BMSK_(HWERRCAUSE3_P) | \
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MK_BMSK_(HWERRCAUSE4_P) )
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/* SWRST Masks */
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#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */
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#ifdef __ADSPBF561__
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# define DOUBLE_FAULT_A 0x0008
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# define DOUBLE_FAULT_B 0x0010
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# define DOUBLE_FAULT 0x0018 /* Core [A|B] Double Fault Causes Reset */
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# define RESET_DOUBLE_A 0x0800
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# define RESET_DOUBLE_B 0x1000
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# define RESET_DOUBLE 0x1800 /* SW Reset Generated By Core [A|B] Double-Fault */
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# define RESET_WDOG_B 0x2000
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# define RESET_WDOG_A 0x4000
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# define RESET_WDOG 0x6000 /* SW Reset Generated By Watchdog [A|B] Timer */
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#else
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# define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */
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# define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */
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# define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */
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#endif
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#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */
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/* SYSCFG Masks */
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#define SSSTEP 0x00000001 /* Supervisor Single Step */
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#define CCEN 0x00000002 /* Cycle Counter Enable */
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#define SNEN 0x00000004 /* Self-Nesting Interrupt Enable */
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#endif
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