upstream u-boot with additional patches for our devices/boards: https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ; Gbit ethernet patch for some LIME2 revisions ; with SPI flash support

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Bin Meng 51050ff0a2 x86: irq: Support discrete PIRQ routing registers via device tree ... Currently both pirq_reg_to_linkno() and pirq_linkno_to_reg() assume consecutive PIRQ routing control registers. But this is not always the case on some platforms. Introduce a new device tree property intel,pirq-regmap to describe how the PIRQ routing register offset is mapped to the link number and adjust the irq router driver to utilize the mapping. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>		6 years ago
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fsp	…
video	…
acpi_s3.h	…
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atomic.h	…
bitops.h	…
bootm.h	…
bootparam.h	…
byteorder.h	…
cache.h	…
cmos_layout.h	…
config.h	…
control_regs.h	…
coreboot_tables.h	…
cpu.h	…
cpu_common.h	…
cpu_x86.h	…
dma-mapping.h	…
e820.h	…
early_cmos.h	…
elf.h	…
global_data.h	…
gpio.h	…
i8254.h	…
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ibmpc.h	…
intel_regs.h	…
interrupt.h	…
io.h	…
ioapic.h	…
ioctl.h	…
irq.h	x86: irq: Support discrete PIRQ routing registers via device tree	6 years ago
ist.h	…
lapic.h	…
linkage.h	…
lpc_common.h	…
me_common.h	…
microcode.h	…
mp.h	…
mpspec.h	…
mrc_common.h	…
mrccache.h	…
msr-index.h	…
msr.h	…
mtrr.h	…
pch_common.h	…
pci.h	…
pirq_routing.h	…
pmu.h	…
pnp_def.h	…
posix_types.h	…
post.h	…
processor-flags.h	…
processor.h	…
ptrace.h	…
report_platform.h	…
scu.h	…
sections.h	…
setjmp.h	…
sfi.h	…
sipi.h	…
speedstep.h	…
spl.h	…
string.h	…
tables.h	…
turbo.h	…
types.h	…
u-boot-x86.h	Define board_quiesce_devices() in a shared location	6 years ago
u-boot.h	…
unaligned.h	…
zimage.h	…