upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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97 lines
2.0 KiB
97 lines
2.0 KiB
config ARCH_LS1021A
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bool
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select SYS_FSL_ERRATUM_A010315
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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select SYS_FSL_DDR_BE
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select SYS_FSL_DDR_VER_50
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_COMPAT_5
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menu "LS102xA architecture"
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depends on ARCH_LS1021A
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config LS1_DEEP_SLEEP
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bool "Deep sleep"
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depends on ARCH_LS1021A
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config MAX_CPUS
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int "Maximum number of CPUs permitted for LS102xA"
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depends on ARCH_LS1021A
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default 2
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help
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Set this number to the maximum number of possible CPUs in the SoC.
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SoCs may have multiple clusters with each cluster may have multiple
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ports. If some ports are reserved but higher ports are used for
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cores, count the reserved ports. This will allocate enough memory
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in spin table to properly handle all cores.
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config NUM_DDR_CONTROLLERS
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int "Maximum DDR controllers"
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default 1
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config SECURE_BOOT
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bool "Secure Boot"
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help
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Enable Freescale Secure Boot feature. Normally selected
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by defconfig. If unsure, do not change.
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config SYS_FSL_ERRATUM_A010315
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bool "Workaround for PCIe erratum A010315"
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config SYS_FSL_SRDS_1
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bool
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config SYS_FSL_SRDS_2
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bool
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config SYS_HAS_SERDES
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bool
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config SYS_FSL_DDR
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bool "Freescale DDR driver"
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help
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Select Freescale General DDR driver, shared between most Freescale
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PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
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based Layerscape SoCs (such as ls2080a).
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config SYS_FSL_DDR_BE
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bool
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default y
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help
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Access DDR registers in big-endian.
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config SYS_FSL_DDR_VER
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int
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default 50 if SYS_FSL_DDR_VER_50
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config SYS_FSL_DDR_VER_50
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bool
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config SYS_FSL_DDRC_ARM_GEN3
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bool
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config SYS_FSL_DDRC_GEN4
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bool
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config SYS_FSL_DDR3
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bool "Freescale DDR3 controller"
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depends on !SYS_FSL_DDR4
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select SYS_FSL_DDR
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select SYS_FSL_DDRC_ARM_GEN3
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help
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Enable Freescale DDR3 controller on ARM-based SoCs.
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config SYS_FSL_DDR4
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bool "Freescale DDR4 controller"
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select SYS_FSL_DDR
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select SYS_FSL_DDRC_GEN4
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help
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Enable Freescale DDR4 controller.
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config SYS_FSL_IFC_BANK_COUNT
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int "Maximum banks of Integrated flash controller"
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depends on ARCH_LS1021A
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default 8
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endmenu
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