upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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712 lines
17 KiB
712 lines
17 KiB
/*
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* Copyright (C) Procsys. All rights reserved.
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* Author: Mushtaq Khan <mushtaq_k@procsys.com>
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* <mushtaqk_921@yahoo.co.in>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* with the reference to ata_piix driver in kernel 2.4.32
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*/
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/*
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* This file contains SATA controller and SATA drive initialization functions
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <pci.h>
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#include <command.h>
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#include <config.h>
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#include <asm/byteorder.h>
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#include <part.h>
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#include <ide.h>
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#include <ata.h>
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#include <sata.h>
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#define DEBUG_SATA 0 /* For debug prints set DEBUG_SATA to 1 */
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#define SATA_DECL
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#define DRV_DECL /* For file specific declarations */
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#include "ata_piix.h"
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/* Macros realted to PCI */
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#define PCI_SATA_BUS 0x00
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#define PCI_SATA_DEV 0x1f
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#define PCI_SATA_FUNC 0x02
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#define PCI_SATA_BASE1 0x10
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#define PCI_SATA_BASE2 0x14
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#define PCI_SATA_BASE3 0x18
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#define PCI_SATA_BASE4 0x1c
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#define PCI_SATA_BASE5 0x20
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#define PCI_PMR 0x90
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#define PCI_PI 0x09
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#define PCI_PCS 0x92
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#define PCI_DMA_CTL 0x48
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#define PORT_PRESENT (1<<0)
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#define PORT_ENABLED (1<<4)
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u32 bdf;
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u32 iobase1; /* Primary cmd block */
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u32 iobase2; /* Primary ctl block */
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u32 iobase3; /* Sec cmd block */
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u32 iobase4; /* sec ctl block */
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u32 iobase5; /* BMDMA*/
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int pci_sata_init(void)
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{
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u32 bus = PCI_SATA_BUS;
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u32 dev = PCI_SATA_DEV;
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u32 fun = PCI_SATA_FUNC;
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u16 cmd = 0;
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u8 lat = 0, pcibios_max_latency = 0xff;
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u8 pmr; /* Port mapping reg */
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u8 pi; /* Prgming Interface reg */
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bdf = PCI_BDF(bus, dev, fun);
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pci_read_config_dword(bdf, PCI_SATA_BASE1, &iobase1);
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pci_read_config_dword(bdf, PCI_SATA_BASE2, &iobase2);
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pci_read_config_dword(bdf, PCI_SATA_BASE3, &iobase3);
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pci_read_config_dword(bdf, PCI_SATA_BASE4, &iobase4);
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pci_read_config_dword(bdf, PCI_SATA_BASE5, &iobase5);
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if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
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(iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
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(iobase5 == 0xFFFFFFFF)) {
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/* ERROR */
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printf("error no base addr for SATA controller\n");
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return 1;
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}
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iobase1 &= 0xFFFFFFFE;
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iobase2 &= 0xFFFFFFFE;
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iobase3 &= 0xFFFFFFFE;
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iobase4 &= 0xFFFFFFFE;
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iobase5 &= 0xFFFFFFFE;
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/* check for mode */
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pci_read_config_byte(bdf, PCI_PMR, &pmr);
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if (pmr > 1) {
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puts("combined mode not supported\n");
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return 1;
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}
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pci_read_config_byte(bdf, PCI_PI, &pi);
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if ((pi & 0x05) != 0x05) {
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puts("Sata is in Legacy mode\n");
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return 1;
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} else
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puts("sata is in Native mode\n");
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/* MASTER CFG AND IO CFG */
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pci_read_config_word(bdf, PCI_COMMAND, &cmd);
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cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
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pci_write_config_word(bdf, PCI_COMMAND, cmd);
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pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
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if (lat < 16)
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lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
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else if (lat > pcibios_max_latency)
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lat = pcibios_max_latency;
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
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return 0;
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}
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int sata_bus_probe(int port_no)
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{
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int orig_mask, mask;
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u16 pcs;
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mask = (PORT_PRESENT << port_no);
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pci_read_config_word(bdf, PCI_PCS, &pcs);
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orig_mask = (int) pcs & 0xff;
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if ((orig_mask & mask) != mask)
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return 0;
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else
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return 1;
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}
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int init_sata(int dev)
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{
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static int done;
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u8 i, rv = 0;
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if (!done)
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done = 1;
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else
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return 0;
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rv = pci_sata_init();
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if (rv == 1) {
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puts("pci initialization failed\n");
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return 1;
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}
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port[0].port_no = 0;
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port[0].ioaddr.cmd_addr = iobase1;
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port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
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iobase2 | ATA_PCI_CTL_OFS;
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port[0].ioaddr.bmdma_addr = iobase5;
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port[1].port_no = 1;
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port[1].ioaddr.cmd_addr = iobase3;
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port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
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iobase4 | ATA_PCI_CTL_OFS;
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port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
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for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++)
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sata_port(&port[i].ioaddr);
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for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
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if (!(sata_bus_probe(i))) {
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port[i].port_state = 0;
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printf("SATA#%d port is not present\n", i);
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} else {
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printf("SATA#%d port is present\n", i);
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if (sata_bus_softreset(i))
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port[i].port_state = 0;
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else
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port[i].port_state = 1;
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}
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}
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for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
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u8 j, devno;
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if (port[i].port_state == 0)
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continue;
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for (j = 0; j < CONFIG_SYS_SATA_DEVS_PER_BUS; j++) {
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sata_identify(i, j);
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set_Feature_cmd(i, j);
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devno = i * CONFIG_SYS_SATA_DEVS_PER_BUS + j;
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if ((sata_dev_desc[devno].lba > 0) &&
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(sata_dev_desc[devno].blksz > 0)) {
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dev_print(&sata_dev_desc[devno]);
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/* initialize partition type */
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init_part(&sata_dev_desc[devno]);
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}
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}
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}
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return 0;
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}
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static inline u8 sata_inb(unsigned long ioaddr)
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{
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return inb(ioaddr);
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}
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static inline void sata_outb(unsigned char val, unsigned long ioaddr)
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{
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outb(val, ioaddr);
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}
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static void output_data(struct sata_ioports *ioaddr, ulong * sect_buf,
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int words)
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{
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outsw(ioaddr->data_addr, sect_buf, words << 1);
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}
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static int input_data(struct sata_ioports *ioaddr, ulong * sect_buf, int words)
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{
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insw(ioaddr->data_addr, sect_buf, words << 1);
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return 0;
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}
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static void sata_cpy(unsigned char *dst, unsigned char *src, unsigned int len)
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{
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unsigned char *end, *last;
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last = dst;
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end = src + len - 1;
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/* reserve space for '\0' */
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if (len < 2)
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goto OUT;
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/* skip leading white space */
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while ((*src) && (src < end) && (*src == ' '))
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++src;
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/* copy string, omitting trailing white space */
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while ((*src) && (src < end)) {
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*dst++ = *src;
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if (*src++ != ' ')
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last = dst;
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}
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OUT:
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*last = '\0';
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}
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int sata_bus_softreset(int num)
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{
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u8 dev = 0, status = 0, i;
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port[num].dev_mask = 0;
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for (i = 0; i < CONFIG_SYS_SATA_DEVS_PER_BUS; i++) {
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if (!(sata_devchk(&port[num].ioaddr, i))) {
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debug("dev_chk failed for dev#%d\n", i);
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} else {
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port[num].dev_mask |= (1 << i);
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debug("dev_chk passed for dev#%d\n", i);
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}
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}
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if (!(port[num].dev_mask)) {
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printf("no devices on port%d\n", num);
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return 1;
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}
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dev_select(&port[num].ioaddr, dev);
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port[num].ctl_reg = 0x08; /* Default value of control reg */
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sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr);
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udelay(10);
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sata_outb(port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
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udelay(10);
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sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr);
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/*
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* spec mandates ">= 2ms" before checking status.
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* We wait 150ms, because that was the magic delay used for
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* ATAPI devices in Hale Landis's ATADRVR, for the period of time
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* between when the ATA command register is written, and then
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* status is checked. Because waiting for "a while" before
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* checking status is fine, post SRST, we perform this magic
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* delay here as well.
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*/
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mdelay(150);
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status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 300);
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while ((status & ATA_BUSY)) {
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mdelay(100);
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status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 3);
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}
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if (status & ATA_BUSY)
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printf("ata%u is slow to respond,plz be patient\n", num);
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while ((status & ATA_BUSY)) {
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mdelay(100);
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status = sata_chk_status(&port[num].ioaddr);
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}
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if (status & ATA_BUSY) {
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printf("ata%u failed to respond : bus reset failed\n", num);
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return 1;
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}
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return 0;
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}
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void sata_identify(int num, int dev)
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{
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u8 cmd = 0, status = 0;
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u8 devno = num * CONFIG_SYS_SATA_DEVS_PER_BUS + dev;
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u16 iobuf[ATA_SECT_SIZE];
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u64 n_sectors = 0;
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u8 mask = 0;
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memset(iobuf, 0, sizeof(iobuf));
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hd_driveid_t *iop = (hd_driveid_t *) iobuf;
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if (dev == 0)
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mask = 0x01;
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else
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mask = 0x02;
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if (!(port[num].dev_mask & mask)) {
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printf("dev%d is not present on port#%d\n", dev, num);
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return;
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}
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printf("port=%d dev=%d\n", num, dev);
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dev_select(&port[num].ioaddr, dev);
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status = 0;
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cmd = ATA_CMD_IDENT; /* Device Identify Command */
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sata_outb(cmd, port[num].ioaddr.command_addr);
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sata_inb(port[num].ioaddr.altstatus_addr);
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udelay(10);
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status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 1000);
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if (status & ATA_ERR) {
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puts("\ndevice not responding\n");
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port[num].dev_mask &= ~mask;
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return;
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}
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input_data(&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
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debug("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
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"86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49],
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iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86],
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iobuf[87], iobuf[88]);
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/* we require LBA and DMA support (bits 8 & 9 of word 49) */
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if (!ata_id_has_dma(iobuf) || !ata_id_has_lba(iobuf))
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debug("ata%u: no dma/lba\n", num);
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ata_dump_id(iobuf);
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if (ata_id_has_lba48(iobuf))
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n_sectors = ata_id_u64(iobuf, 100);
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else
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n_sectors = ata_id_u32(iobuf, 60);
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debug("no. of sectors %u\n", ata_id_u64(iobuf, 100));
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debug("no. of sectors %u\n", ata_id_u32(iobuf, 60));
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if (n_sectors == 0) {
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port[num].dev_mask &= ~mask;
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return;
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}
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sata_cpy((unsigned char *)sata_dev_desc[devno].revision, iop->fw_rev,
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sizeof(sata_dev_desc[devno].revision));
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sata_cpy((unsigned char *)sata_dev_desc[devno].vendor, iop->model,
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sizeof(sata_dev_desc[devno].vendor));
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sata_cpy((unsigned char *)sata_dev_desc[devno].product, iop->serial_no,
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sizeof(sata_dev_desc[devno].product));
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strswab(sata_dev_desc[devno].revision);
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strswab(sata_dev_desc[devno].vendor);
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if ((iop->config & 0x0080) == 0x0080)
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sata_dev_desc[devno].removable = 1;
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else
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sata_dev_desc[devno].removable = 0;
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sata_dev_desc[devno].lba = iop->lba_capacity;
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debug("lba=0x%x", sata_dev_desc[devno].lba);
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#ifdef CONFIG_LBA48
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if (iop->command_set_2 & 0x0400) {
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sata_dev_desc[devno].lba48 = 1;
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lba = (unsigned long long) iop->lba48_capacity[0] |
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((unsigned long long) iop->lba48_capacity[1] << 16) |
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((unsigned long long) iop->lba48_capacity[2] << 32) |
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((unsigned long long) iop->lba48_capacity[3] << 48);
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} else {
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sata_dev_desc[devno].lba48 = 0;
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}
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#endif
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/* assuming HD */
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sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
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sata_dev_desc[devno].blksz = ATA_BLOCKSIZE;
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sata_dev_desc[devno].log2blksz = LOG2(sata_dev_desc[devno].blksz);
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sata_dev_desc[devno].lun = 0; /* just to fill something in... */
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}
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void set_Feature_cmd(int num, int dev)
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{
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u8 mask = 0x00, status = 0;
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if (dev == 0)
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mask = 0x01;
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else
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mask = 0x02;
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if (!(port[num].dev_mask & mask)) {
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debug("dev%d is not present on port#%d\n", dev, num);
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return;
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}
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dev_select(&port[num].ioaddr, dev);
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sata_outb(SETFEATURES_XFER, port[num].ioaddr.feature_addr);
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sata_outb(XFER_PIO_4, port[num].ioaddr.nsect_addr);
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sata_outb(0, port[num].ioaddr.lbal_addr);
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sata_outb(0, port[num].ioaddr.lbam_addr);
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sata_outb(0, port[num].ioaddr.lbah_addr);
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sata_outb(ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
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sata_outb(ATA_CMD_SETF, port[num].ioaddr.command_addr);
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udelay(50);
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mdelay(150);
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status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 5000);
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if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) {
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printf("Error : status 0x%02x\n", status);
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port[num].dev_mask &= ~mask;
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}
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}
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void sata_port(struct sata_ioports *ioport)
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{
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ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
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ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
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ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
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ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
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ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
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ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
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ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
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ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
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ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
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ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
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}
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int sata_devchk(struct sata_ioports *ioaddr, int dev)
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{
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u8 nsect, lbal;
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dev_select(ioaddr, dev);
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sata_outb(0x55, ioaddr->nsect_addr);
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sata_outb(0xaa, ioaddr->lbal_addr);
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sata_outb(0xaa, ioaddr->nsect_addr);
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sata_outb(0x55, ioaddr->lbal_addr);
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sata_outb(0x55, ioaddr->nsect_addr);
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sata_outb(0xaa, ioaddr->lbal_addr);
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nsect = sata_inb(ioaddr->nsect_addr);
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lbal = sata_inb(ioaddr->lbal_addr);
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if ((nsect == 0x55) && (lbal == 0xaa))
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return 1; /* we found a device */
|
|
else
|
|
return 0; /* nothing found */
|
|
}
|
|
|
|
void dev_select(struct sata_ioports *ioaddr, int dev)
|
|
{
|
|
u8 tmp = 0;
|
|
|
|
if (dev == 0)
|
|
tmp = ATA_DEVICE_OBS;
|
|
else
|
|
tmp = ATA_DEVICE_OBS | ATA_DEV1;
|
|
|
|
sata_outb(tmp, ioaddr->device_addr);
|
|
sata_inb(ioaddr->altstatus_addr);
|
|
udelay(5);
|
|
}
|
|
|
|
u8 sata_busy_wait(struct sata_ioports *ioaddr, int bits, unsigned int max)
|
|
{
|
|
u8 status;
|
|
|
|
do {
|
|
udelay(1000);
|
|
status = sata_chk_status(ioaddr);
|
|
max--;
|
|
} while ((status & bits) && (max > 0));
|
|
|
|
return status;
|
|
}
|
|
|
|
u8 sata_chk_status(struct sata_ioports *ioaddr)
|
|
{
|
|
return sata_inb(ioaddr->status_addr);
|
|
}
|
|
|
|
|
|
ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buff)
|
|
{
|
|
ulong n = 0, *buffer = (ulong *)buff;
|
|
u8 dev = 0, num = 0, mask = 0, status = 0;
|
|
|
|
#ifdef CONFIG_LBA48
|
|
unsigned char lba48 = 0;
|
|
|
|
if (blknr & 0x0000fffff0000000) {
|
|
if (!sata_dev_desc[devno].lba48) {
|
|
printf("Drive doesn't support 48-bit addressing\n");
|
|
return 0;
|
|
}
|
|
/* more than 28 bits used, use 48bit mode */
|
|
lba48 = 1;
|
|
}
|
|
#endif
|
|
/* Port Number */
|
|
num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
|
|
/* dev on the port */
|
|
if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
|
|
dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
|
|
else
|
|
dev = device;
|
|
|
|
if (dev == 0)
|
|
mask = 0x01;
|
|
else
|
|
mask = 0x02;
|
|
|
|
if (!(port[num].dev_mask & mask)) {
|
|
printf("dev%d is not present on port#%d\n", dev, num);
|
|
return 0;
|
|
}
|
|
|
|
/* Select device */
|
|
dev_select(&port[num].ioaddr, dev);
|
|
|
|
status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
|
|
if (status & ATA_BUSY) {
|
|
printf("ata%u failed to respond\n", port[num].port_no);
|
|
return n;
|
|
}
|
|
while (blkcnt-- > 0) {
|
|
status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
|
|
if (status & ATA_BUSY) {
|
|
printf("ata%u failed to respond\n", 0);
|
|
return n;
|
|
}
|
|
#ifdef CONFIG_LBA48
|
|
if (lba48) {
|
|
/* write high bits */
|
|
sata_outb(0, port[num].ioaddr.nsect_addr);
|
|
sata_outb((blknr >> 24) & 0xFF,
|
|
port[num].ioaddr.lbal_addr);
|
|
sata_outb((blknr >> 32) & 0xFF,
|
|
port[num].ioaddr.lbam_addr);
|
|
sata_outb((blknr >> 40) & 0xFF,
|
|
port[num].ioaddr.lbah_addr);
|
|
}
|
|
#endif
|
|
sata_outb(1, port[num].ioaddr.nsect_addr);
|
|
sata_outb(((blknr) >> 0) & 0xFF,
|
|
port[num].ioaddr.lbal_addr);
|
|
sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
|
|
sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
|
|
|
|
#ifdef CONFIG_LBA48
|
|
if (lba48) {
|
|
sata_outb(ATA_LBA, port[num].ioaddr.device_addr);
|
|
sata_outb(ATA_CMD_READ_EXT,
|
|
port[num].ioaddr.command_addr);
|
|
} else
|
|
#endif
|
|
{
|
|
sata_outb(ATA_LBA | ((blknr >> 24) & 0xF),
|
|
port[num].ioaddr.device_addr);
|
|
sata_outb(ATA_CMD_READ,
|
|
port[num].ioaddr.command_addr);
|
|
}
|
|
|
|
mdelay(50);
|
|
/* may take up to 4 sec */
|
|
status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000);
|
|
|
|
if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
|
|
!= ATA_STAT_DRQ) {
|
|
u8 err = 0;
|
|
|
|
printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
|
|
device, (ulong) blknr, status);
|
|
err = sata_inb(port[num].ioaddr.error_addr);
|
|
printf("Error reg = 0x%x\n", err);
|
|
return n;
|
|
}
|
|
input_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS);
|
|
sata_inb(port[num].ioaddr.altstatus_addr);
|
|
udelay(50);
|
|
|
|
++n;
|
|
++blknr;
|
|
buffer += ATA_SECTORWORDS;
|
|
}
|
|
return n;
|
|
}
|
|
|
|
ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, const void *buff)
|
|
{
|
|
ulong n = 0, *buffer = (ulong *)buff;
|
|
unsigned char status = 0, num = 0, dev = 0, mask = 0;
|
|
|
|
#ifdef CONFIG_LBA48
|
|
unsigned char lba48 = 0;
|
|
|
|
if (blknr & 0x0000fffff0000000) {
|
|
if (!sata_dev_desc[devno].lba48) {
|
|
printf("Drive doesn't support 48-bit addressing\n");
|
|
return 0;
|
|
}
|
|
/* more than 28 bits used, use 48bit mode */
|
|
lba48 = 1;
|
|
}
|
|
#endif
|
|
/* Port Number */
|
|
num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
|
|
/* dev on the Port */
|
|
if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
|
|
dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
|
|
else
|
|
dev = device;
|
|
|
|
if (dev == 0)
|
|
mask = 0x01;
|
|
else
|
|
mask = 0x02;
|
|
|
|
/* Select device */
|
|
dev_select(&port[num].ioaddr, dev);
|
|
|
|
status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
|
|
if (status & ATA_BUSY) {
|
|
printf("ata%u failed to respond\n", port[num].port_no);
|
|
return n;
|
|
}
|
|
|
|
while (blkcnt-- > 0) {
|
|
status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
|
|
if (status & ATA_BUSY) {
|
|
printf("ata%u failed to respond\n",
|
|
port[num].port_no);
|
|
return n;
|
|
}
|
|
#ifdef CONFIG_LBA48
|
|
if (lba48) {
|
|
/* write high bits */
|
|
sata_outb(0, port[num].ioaddr.nsect_addr);
|
|
sata_outb((blknr >> 24) & 0xFF,
|
|
port[num].ioaddr.lbal_addr);
|
|
sata_outb((blknr >> 32) & 0xFF,
|
|
port[num].ioaddr.lbam_addr);
|
|
sata_outb((blknr >> 40) & 0xFF,
|
|
port[num].ioaddr.lbah_addr);
|
|
}
|
|
#endif
|
|
sata_outb(1, port[num].ioaddr.nsect_addr);
|
|
sata_outb((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
|
|
sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
|
|
sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
|
|
#ifdef CONFIG_LBA48
|
|
if (lba48) {
|
|
sata_outb(ATA_LBA, port[num].ioaddr.device_addr);
|
|
sata_outb(ATA_CMD_WRITE_EXT,
|
|
port[num].ioaddr.command_addr);
|
|
} else
|
|
#endif
|
|
{
|
|
sata_outb(ATA_LBA | ((blknr >> 24) & 0xF),
|
|
port[num].ioaddr.device_addr);
|
|
sata_outb(ATA_CMD_WRITE,
|
|
port[num].ioaddr.command_addr);
|
|
}
|
|
|
|
mdelay(50);
|
|
/* may take up to 4 sec */
|
|
status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000);
|
|
if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
|
|
!= ATA_STAT_DRQ) {
|
|
printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
|
|
device, (ulong) blknr, status);
|
|
return n;
|
|
}
|
|
|
|
output_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS);
|
|
sata_inb(port[num].ioaddr.altstatus_addr);
|
|
udelay(50);
|
|
|
|
++n;
|
|
++blknr;
|
|
buffer += ATA_SECTORWORDS;
|
|
}
|
|
return n;
|
|
}
|
|
|
|
int scan_sata(int dev)
|
|
{
|
|
return 0;
|
|
}
|
|
|