upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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419 lines
10 KiB
419 lines
10 KiB
/*
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* (C) Copyright 2007-2009
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* based on work by Anne Sophie Harnois <anne-sophie.harnois@nextream.fr>
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*
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* (C) Copyright 2001
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* Bill Hunter, Wave 7 Optics, williamhunter@mediaone.net
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/ppc4xx.h>
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#include <asm/ppc4xx-i2c.h>
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#include <i2c.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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static inline struct ppc4xx_i2c *ppc4xx_get_i2c(int hwadapnr)
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{
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unsigned long base;
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#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
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defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
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defined(CONFIG_460EX) || defined(CONFIG_460GT)
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base = CONFIG_SYS_PERIPHERAL_BASE + 0x00000700 + (hwadapnr * 0x100);
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#elif defined(CONFIG_440) || defined(CONFIG_405EX)
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/* all remaining 440 variants */
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base = CONFIG_SYS_PERIPHERAL_BASE + 0x00000400 + (hwadapnr * 0x100);
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#else
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/* all 405 variants */
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base = 0xEF600500 + (hwadapnr * 0x100);
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#endif
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return (struct ppc4xx_i2c *)base;
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}
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static void _i2c_bus_reset(struct i2c_adapter *adap)
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{
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struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
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int i;
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u8 dc;
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/* Reset status register */
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/* write 1 in SCMP and IRQA to clear these fields */
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out_8(&i2c->sts, 0x0A);
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/* write 1 in IRQP IRQD LA ICT XFRA to clear these fields */
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out_8(&i2c->extsts, 0x8F);
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/* Place chip in the reset state */
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out_8(&i2c->xtcntlss, IIC_XTCNTLSS_SRST);
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/* Check if bus is free */
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dc = in_8(&i2c->directcntl);
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if (!DIRCTNL_FREE(dc)){
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/* Try to set bus free state */
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out_8(&i2c->directcntl, IIC_DIRCNTL_SDAC | IIC_DIRCNTL_SCC);
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/* Wait until we regain bus control */
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for (i = 0; i < 100; ++i) {
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dc = in_8(&i2c->directcntl);
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if (DIRCTNL_FREE(dc))
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break;
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/* Toggle SCL line */
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dc ^= IIC_DIRCNTL_SCC;
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out_8(&i2c->directcntl, dc);
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udelay(10);
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dc ^= IIC_DIRCNTL_SCC;
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out_8(&i2c->directcntl, dc);
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}
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}
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/* Remove reset */
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out_8(&i2c->xtcntlss, 0);
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}
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static void ppc4xx_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
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{
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struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
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int val, divisor;
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#ifdef CONFIG_SYS_I2C_INIT_BOARD
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/*
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* Call board specific i2c bus reset routine before accessing the
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* environment, which might be in a chip on that bus. For details
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* about this problem see doc/I2C_Edge_Conditions.
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*/
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i2c_init_board();
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#endif
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/* Handle possible failed I2C state */
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/* FIXME: put this into i2c_init_board()? */
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_i2c_bus_reset(adap);
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/* clear lo master address */
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out_8(&i2c->lmadr, 0);
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/* clear hi master address */
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out_8(&i2c->hmadr, 0);
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/* clear lo slave address */
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out_8(&i2c->lsadr, 0);
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/* clear hi slave address */
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out_8(&i2c->hsadr, 0);
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/* Clock divide Register */
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/* set divisor according to freq_opb */
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divisor = (get_OPB_freq() - 1) / 10000000;
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if (divisor == 0)
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divisor = 1;
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out_8(&i2c->clkdiv, divisor);
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/* no interrupts */
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out_8(&i2c->intrmsk, 0);
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/* clear transfer count */
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out_8(&i2c->xfrcnt, 0);
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/* clear extended control & stat */
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/* write 1 in SRC SRS SWC SWS to clear these fields */
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out_8(&i2c->xtcntlss, 0xF0);
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/* Mode Control Register
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Flush Slave/Master data buffer */
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out_8(&i2c->mdcntl, IIC_MDCNTL_FSDB | IIC_MDCNTL_FMDB);
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val = in_8(&i2c->mdcntl);
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/* Ignore General Call, slave transfers are ignored,
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* disable interrupts, exit unknown bus state, enable hold
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* SCL 100kHz normaly or FastMode for 400kHz and above
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*/
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val |= IIC_MDCNTL_EUBS | IIC_MDCNTL_HSCL;
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if (speed >= 400000)
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val |= IIC_MDCNTL_FSM;
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out_8(&i2c->mdcntl, val);
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/* clear control reg */
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out_8(&i2c->cntl, 0x00);
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}
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/*
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* This code tries to use the features of the 405GP i2c
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* controller. It will transfer up to 4 bytes in one pass
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* on the loop. It only does out_8((u8 *)lbz) to the buffer when it
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* is possible to do out16(lhz) transfers.
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*
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* cmd_type is 0 for write 1 for read.
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*
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* addr_len can take any value from 0-255, it is only limited
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* by the char, we could make it larger if needed. If it is
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* 0 we skip the address write cycle.
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*
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* Typical case is a Write of an addr followd by a Read. The
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* IBM FAQ does not cover this. On the last byte of the write
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* we don't set the creg CHT bit, and on the first bytes of the
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* read we set the RPST bit.
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*
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* It does not support address only transfers, there must be
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* a data part. If you want to write the address yourself, put
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* it in the data pointer.
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*
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* It does not support transfer to/from address 0.
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*
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* It does not check XFRCNT.
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*/
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static int _i2c_transfer(struct i2c_adapter *adap,
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unsigned char cmd_type,
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unsigned char chip,
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unsigned char addr[],
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unsigned char addr_len,
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unsigned char data[],
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unsigned short data_len)
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{
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struct ppc4xx_i2c *i2c = ppc4xx_get_i2c(adap->hwadapnr);
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u8 *ptr;
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int reading;
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int tran, cnt;
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int result;
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int status;
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int i;
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u8 creg;
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if (data == 0 || data_len == 0) {
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/* Don't support data transfer of no length or to address 0 */
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printf( "i2c_transfer: bad call\n" );
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return IIC_NOK;
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}
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if (addr && addr_len) {
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ptr = addr;
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cnt = addr_len;
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reading = 0;
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} else {
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ptr = data;
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cnt = data_len;
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reading = cmd_type;
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}
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/* Clear Stop Complete Bit */
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out_8(&i2c->sts, IIC_STS_SCMP);
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/* Check init */
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i = 10;
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do {
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/* Get status */
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status = in_8(&i2c->sts);
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i--;
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} while ((status & IIC_STS_PT) && (i > 0));
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if (status & IIC_STS_PT) {
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result = IIC_NOK_TOUT;
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return(result);
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}
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/* flush the Master/Slave Databuffers */
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out_8(&i2c->mdcntl, in_8(&i2c->mdcntl) |
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IIC_MDCNTL_FMDB | IIC_MDCNTL_FSDB);
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/* need to wait 4 OPB clocks? code below should take that long */
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/* 7-bit adressing */
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out_8(&i2c->hmadr, 0);
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out_8(&i2c->lmadr, chip);
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tran = 0;
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result = IIC_OK;
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creg = 0;
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while (tran != cnt && (result == IIC_OK)) {
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int bc,j;
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/*
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* Control register =
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* Normal transfer, 7-bits adressing, Transfer up to
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* bc bytes, Normal start, Transfer is a sequence of transfers
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*/
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creg |= IIC_CNTL_PT;
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bc = (cnt - tran) > 4 ? 4 : cnt - tran;
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creg |= (bc - 1) << 4;
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/* if the real cmd type is write continue trans */
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if ((!cmd_type && (ptr == addr)) || ((tran + bc) != cnt))
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creg |= IIC_CNTL_CHT;
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if (reading) {
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creg |= IIC_CNTL_READ;
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} else {
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for(j = 0; j < bc; j++) {
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/* Set buffer */
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out_8(&i2c->mdbuf, ptr[tran + j]);
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}
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}
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out_8(&i2c->cntl, creg);
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/*
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* Transfer is in progress
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* we have to wait for upto 5 bytes of data
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* 1 byte chip address+r/w bit then bc bytes
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* of data.
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* udelay(10) is 1 bit time at 100khz
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* Doubled for slop. 20 is too small.
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*/
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i = 2 * 5 * 8;
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do {
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/* Get status */
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status = in_8(&i2c->sts);
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udelay(10);
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i--;
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} while ((status & IIC_STS_PT) && !(status & IIC_STS_ERR) &&
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(i > 0));
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if (status & IIC_STS_ERR) {
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result = IIC_NOK;
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status = in_8(&i2c->extsts);
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/* Lost arbitration? */
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if (status & IIC_EXTSTS_LA)
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result = IIC_NOK_LA;
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/* Incomplete transfer? */
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if (status & IIC_EXTSTS_ICT)
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result = IIC_NOK_ICT;
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/* Transfer aborted? */
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if (status & IIC_EXTSTS_XFRA)
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result = IIC_NOK_XFRA;
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} else if ( status & IIC_STS_PT) {
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result = IIC_NOK_TOUT;
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}
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/* Command is reading => get buffer */
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if ((reading) && (result == IIC_OK)) {
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/* Are there data in buffer */
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if (status & IIC_STS_MDBS) {
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/*
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* even if we have data we have to wait 4OPB
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* clocks for it to hit the front of the FIFO,
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* after that we can just read. We should check
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* XFCNT here and if the FIFO is full there is
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* no need to wait.
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*/
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udelay(1);
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for (j = 0; j < bc; j++)
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ptr[tran + j] = in_8(&i2c->mdbuf);
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} else
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result = IIC_NOK_DATA;
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}
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creg = 0;
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tran += bc;
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if (ptr == addr && tran == cnt) {
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ptr = data;
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cnt = data_len;
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tran = 0;
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reading = cmd_type;
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if (reading)
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creg = IIC_CNTL_RPST;
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}
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}
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return result;
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}
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static int ppc4xx_i2c_probe(struct i2c_adapter *adap, uchar chip)
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{
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uchar buf[1];
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buf[0] = 0;
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/*
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* What is needed is to send the chip address and verify that the
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* address was <ACK>ed (i.e. there was a chip at that address which
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* drove the data line low).
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*/
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return (_i2c_transfer(adap, 1, chip << 1, 0, 0, buf, 1) != 0);
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}
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static int ppc4xx_i2c_transfer(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *buffer, int len, int read)
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{
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uchar xaddr[4];
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int ret;
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if (alen > 4) {
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printf("I2C: addr len %d not supported\n", alen);
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return 1;
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}
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if (alen > 0) {
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xaddr[0] = (addr >> 24) & 0xFF;
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xaddr[1] = (addr >> 16) & 0xFF;
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xaddr[2] = (addr >> 8) & 0xFF;
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xaddr[3] = addr & 0xFF;
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}
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#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
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/*
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* EEPROM chips that implement "address overflow" are ones
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* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
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* address and the extra bits end up in the "chip address"
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* bit slots. This makes a 24WC08 (1Kbyte) chip look like
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* four 256 byte chips.
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*
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* Note that we consider the length of the address field to
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* still be one byte because the extra address bits are
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* hidden in the chip address.
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*/
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if (alen > 0)
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chip |= ((addr >> (alen * 8)) &
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CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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#endif
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ret = _i2c_transfer(adap, read, chip << 1, &xaddr[4 - alen], alen,
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buffer, len);
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if (ret) {
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printf("I2C %s: failed %d\n", read ? "read" : "write", ret);
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return 1;
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}
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return 0;
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}
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static int ppc4xx_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *buffer, int len)
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{
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return ppc4xx_i2c_transfer(adap, chip, addr, alen, buffer, len, 1);
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}
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static int ppc4xx_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *buffer, int len)
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{
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return ppc4xx_i2c_transfer(adap, chip, addr, alen, buffer, len, 0);
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}
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static unsigned int ppc4xx_i2c_set_bus_speed(struct i2c_adapter *adap,
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unsigned int speed)
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{
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if (speed != adap->speed)
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return -1;
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return speed;
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}
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/*
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* Register ppc4xx i2c adapters
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*/
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#ifdef CONFIG_SYS_I2C_PPC4XX_CH0
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U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_0, ppc4xx_i2c_init, ppc4xx_i2c_probe,
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ppc4xx_i2c_read, ppc4xx_i2c_write,
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ppc4xx_i2c_set_bus_speed,
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CONFIG_SYS_I2C_PPC4XX_SPEED_0,
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CONFIG_SYS_I2C_PPC4XX_SLAVE_0, 0)
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#endif
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#ifdef CONFIG_SYS_I2C_PPC4XX_CH1
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U_BOOT_I2C_ADAP_COMPLETE(ppc4xx_1, ppc4xx_i2c_init, ppc4xx_i2c_probe,
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ppc4xx_i2c_read, ppc4xx_i2c_write,
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ppc4xx_i2c_set_bus_speed,
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CONFIG_SYS_I2C_PPC4XX_SPEED_1,
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CONFIG_SYS_I2C_PPC4XX_SLAVE_1, 1)
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#endif
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