upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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63 lines
1.3 KiB
63 lines
1.3 KiB
/*
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* (C) Copyright 2013 Inc.
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*
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* Xilinx Zynq SD Host Controller Interface
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fdtdec.h>
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#include <libfdt.h>
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#include <malloc.h>
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#include <sdhci.h>
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#include <asm/arch/sys_proto.h>
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int zynq_sdhci_init(u32 regbase)
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{
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struct sdhci_host *host = NULL;
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host = (struct sdhci_host *)malloc(sizeof(struct sdhci_host));
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if (!host) {
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printf("zynq_sdhci_init: sdhci_host malloc fail\n");
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return 1;
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}
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host->name = "zynq_sdhci";
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host->ioaddr = (void *)regbase;
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host->quirks = SDHCI_QUIRK_NO_CD | SDHCI_QUIRK_WAIT_SEND_CMD |
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SDHCI_QUIRK_BROKEN_R1B;
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host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
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host->host_caps = MMC_MODE_HC;
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add_sdhci(host, 52000000, 52000000 >> 9);
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return 0;
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}
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#ifdef CONFIG_OF_CONTROL
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int zynq_sdhci_of_init(const void *blob)
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{
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int offset = 0;
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u32 ret = 0;
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u32 reg;
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debug("ZYNQ SDHCI: Initialization\n");
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do {
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offset = fdt_node_offset_by_compatible(blob, offset,
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"arasan,sdhci-8.9a");
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if (offset != -1) {
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reg = fdtdec_get_addr(blob, offset, "reg");
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if (reg != FDT_ADDR_T_NONE) {
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ret |= zynq_sdhci_init(reg);
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} else {
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debug("ZYNQ SDHCI: Can't get base address\n");
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return -1;
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}
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}
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} while (offset != -1);
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return ret;
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}
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#endif
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