upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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473 lines
8.0 KiB
473 lines
8.0 KiB
/*
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* (C) Copyright 2007
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Author: Igor Lisitsin <igor@emcraft.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <post.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#if CONFIG_POST & CONFIG_SYS_POST_CACHE
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.text
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/*
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* All 44x variants deal with cache management differently
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* because they have the address translation always enabled.
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* The 40x ppc's don't use address translation in U-Boot at all,
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* so we have to distinguish here between 40x and 44x.
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*/
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#ifdef CONFIG_440
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/* void cache_post_disable (int tlb)
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*/
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cache_post_disable:
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tlbre r0, r3, 0x0002
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ori r0, r0, TLB_WORD2_I_ENABLE@l
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tlbwe r0, r3, 0x0002
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sync
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isync
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blr
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/* void cache_post_wt (int tlb)
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*/
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cache_post_wt:
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tlbre r0, r3, 0x0002
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ori r0, r0, TLB_WORD2_W_ENABLE@l
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andi. r0, r0, ~TLB_WORD2_I_ENABLE@l
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tlbwe r0, r3, 0x0002
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sync
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isync
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blr
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/* void cache_post_wb (int tlb)
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*/
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cache_post_wb:
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tlbre r0, r3, 0x0002
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andi. r0, r0, ~TLB_WORD2_W_ENABLE@l
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andi. r0, r0, ~TLB_WORD2_I_ENABLE@l
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tlbwe r0, r3, 0x0002
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sync
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isync
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blr
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#else
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/* void cache_post_disable (int tlb)
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*/
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cache_post_disable:
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lis r0, 0x0000
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ori r0, r0, 0x0000
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mtdccr r0
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sync
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isync
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blr
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/* void cache_post_wt (int tlb)
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*/
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cache_post_wt:
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lis r0, 0x8000
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ori r0, r0, 0x0000
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mtdccr r0
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lis r0, 0x8000
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ori r0, r0, 0x0000
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mtdcwr r0
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sync
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isync
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blr
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/* void cache_post_wb (int tlb)
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*/
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cache_post_wb:
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lis r0, 0x8000
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ori r0, r0, 0x0000
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mtdccr r0
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lis r0, 0x0000
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ori r0, r0, 0x0000
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mtdcwr r0
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sync
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isync
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blr
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#endif
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/* void cache_post_dinvalidate (void *p, int size)
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*/
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cache_post_dinvalidate:
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dcbi r0, r3
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addi r3, r3, CONFIG_SYS_CACHELINE_SIZE
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subic. r4, r4, CONFIG_SYS_CACHELINE_SIZE
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bgt cache_post_dinvalidate
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sync
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blr
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/* void cache_post_dstore (void *p, int size)
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*/
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cache_post_dstore:
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dcbst r0, r3
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addi r3, r3, CONFIG_SYS_CACHELINE_SIZE
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subic. r4, r4, CONFIG_SYS_CACHELINE_SIZE
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bgt cache_post_dstore
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sync
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blr
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/* void cache_post_dtouch (void *p, int size)
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*/
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cache_post_dtouch:
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dcbt r0, r3
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addi r3, r3, CONFIG_SYS_CACHELINE_SIZE
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subic. r4, r4, CONFIG_SYS_CACHELINE_SIZE
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bgt cache_post_dtouch
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sync
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blr
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/* void cache_post_iinvalidate (void)
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*/
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cache_post_iinvalidate:
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iccci r0, r0
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sync
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blr
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/* void cache_post_memset (void *p, int val, int size)
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*/
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cache_post_memset:
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mtctr r5
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1:
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stb r4, 0(r3)
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addi r3, r3, 1
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bdnz 1b
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blr
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/* int cache_post_check (void *p, int size)
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*/
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cache_post_check:
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mtctr r4
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1:
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lbz r0, 0(r3)
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addi r3, r3, 1
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cmpwi r0, 0xff
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bne 2f
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bdnz 1b
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li r3, 0
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blr
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2:
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li r3, -1
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blr
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#define CACHE_POST_DISABLE() \
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mr r3, r10; \
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bl cache_post_disable
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#define CACHE_POST_WT() \
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mr r3, r10; \
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bl cache_post_wt
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#define CACHE_POST_WB() \
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mr r3, r10; \
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bl cache_post_wb
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#define CACHE_POST_DINVALIDATE() \
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mr r3, r11; \
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mr r4, r12; \
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bl cache_post_dinvalidate
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#define CACHE_POST_DFLUSH() \
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mr r3, r11; \
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mr r4, r12; \
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bl cache_post_dflush
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#define CACHE_POST_DSTORE() \
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mr r3, r11; \
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mr r4, r12; \
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bl cache_post_dstore
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#define CACHE_POST_DTOUCH() \
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mr r3, r11; \
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mr r4, r12; \
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bl cache_post_dtouch
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#define CACHE_POST_IINVALIDATE() \
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bl cache_post_iinvalidate
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#define CACHE_POST_MEMSET(val) \
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mr r3, r11; \
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li r4, val; \
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mr r5, r12; \
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bl cache_post_memset
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#define CACHE_POST_CHECK() \
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mr r3, r11; \
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mr r4, r12; \
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bl cache_post_check; \
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mr r13, r3
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/*
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* Write and read 0xff pattern with caching enabled.
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*/
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.global cache_post_test1
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cache_post_test1:
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mflr r9
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mr r10, r3 /* tlb */
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mr r11, r4 /* p */
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mr r12, r5 /* size */
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CACHE_POST_WB()
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CACHE_POST_DINVALIDATE()
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/* Write the negative pattern to the test area */
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CACHE_POST_MEMSET(0xff)
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/* Read the test area */
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CACHE_POST_CHECK()
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CACHE_POST_DINVALIDATE()
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CACHE_POST_DISABLE()
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mr r3, r13
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mtlr r9
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blr
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/*
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* Write zeroes with caching enabled.
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* Write 0xff pattern with caching disabled.
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* Read 0xff pattern with caching enabled.
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*/
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.global cache_post_test2
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cache_post_test2:
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mflr r9
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mr r10, r3 /* tlb */
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mr r11, r4 /* p */
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mr r12, r5 /* size */
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CACHE_POST_WB()
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CACHE_POST_DINVALIDATE()
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/* Write the zero pattern to the test area */
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CACHE_POST_MEMSET(0)
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CACHE_POST_DINVALIDATE()
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CACHE_POST_DISABLE()
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/* Write the negative pattern to the test area */
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CACHE_POST_MEMSET(0xff)
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CACHE_POST_WB()
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/* Read the test area */
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CACHE_POST_CHECK()
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CACHE_POST_DINVALIDATE()
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CACHE_POST_DISABLE()
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mr r3, r13
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mtlr r9
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blr
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/*
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* Write-through mode test.
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* Write zeroes, store the cache, write 0xff pattern.
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* Invalidate the cache.
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* Check that 0xff pattern is read.
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*/
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.global cache_post_test3
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cache_post_test3:
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mflr r9
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mr r10, r3 /* tlb */
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mr r11, r4 /* p */
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mr r12, r5 /* size */
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CACHE_POST_WT()
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CACHE_POST_DINVALIDATE()
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/* Cache the test area */
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CACHE_POST_DTOUCH()
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/* Write the zero pattern to the test area */
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CACHE_POST_MEMSET(0)
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CACHE_POST_DSTORE()
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/* Write the negative pattern to the test area */
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CACHE_POST_MEMSET(0xff)
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CACHE_POST_DINVALIDATE()
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CACHE_POST_DISABLE()
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/* Read the test area */
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CACHE_POST_CHECK()
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mr r3, r13
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mtlr r9
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blr
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/*
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* Write-back mode test.
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* Write 0xff pattern, store the cache, write zeroes.
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* Invalidate the cache.
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* Check that 0xff pattern is read.
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*/
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.global cache_post_test4
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cache_post_test4:
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mflr r9
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mr r10, r3 /* tlb */
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mr r11, r4 /* p */
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mr r12, r5 /* size */
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CACHE_POST_WB()
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CACHE_POST_DINVALIDATE()
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/* Cache the test area */
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CACHE_POST_DTOUCH()
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/* Write the negative pattern to the test area */
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CACHE_POST_MEMSET(0xff)
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CACHE_POST_DSTORE()
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/* Write the zero pattern to the test area */
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CACHE_POST_MEMSET(0)
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CACHE_POST_DINVALIDATE()
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CACHE_POST_DISABLE()
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/* Read the test area */
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CACHE_POST_CHECK()
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mr r3, r13
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mtlr r9
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blr
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/*
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* Load the test instructions into the instruction cache.
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* Replace the test instructions.
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* Check that the original instructions are executed.
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*/
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.global cache_post_test5
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cache_post_test5:
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mflr r9
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mr r10, r3 /* tlb */
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mr r11, r4 /* p */
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mr r12, r5 /* size */
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CACHE_POST_WT()
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CACHE_POST_IINVALIDATE()
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/* Compute r13 = cache_post_test_inst */
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bl cache_post_test5_reloc
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cache_post_test5_reloc:
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mflr r13
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lis r0, (cache_post_test_inst - cache_post_test5_reloc)@h
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ori r0, r0, (cache_post_test_inst - cache_post_test5_reloc)@l
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add r13, r13, r0
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/* Copy the test instructions to the test area */
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lwz r0, 0(r13)
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stw r0, 0(r11)
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lwz r0, 8(r13)
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stw r0, 4(r11)
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sync
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/* Invalidate the cache line */
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icbi r0, r11
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sync
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isync
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/* Execute the test instructions */
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mtlr r11
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blrl
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/* Replace the test instruction */
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lwz r0, 4(r13)
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stw r0, 0(r11)
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sync
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/* Do not invalidate the cache line */
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isync
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/* Execute the test instructions */
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mtlr r11
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blrl
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mr r13, r3
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CACHE_POST_IINVALIDATE()
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CACHE_POST_DINVALIDATE()
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CACHE_POST_DISABLE()
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mr r3, r13
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mtlr r9
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blr
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/*
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* Load the test instructions into the instruction cache.
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* Replace the test instructions and invalidate the cache.
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* Check that the replaced instructions are executed.
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*/
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.global cache_post_test6
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cache_post_test6:
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mflr r9
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mr r10, r3 /* tlb */
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mr r11, r4 /* p */
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mr r12, r5 /* size */
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CACHE_POST_WT()
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CACHE_POST_IINVALIDATE()
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/* Compute r13 = cache_post_test_inst */
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bl cache_post_test6_reloc
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cache_post_test6_reloc:
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mflr r13
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lis r0, (cache_post_test_inst - cache_post_test6_reloc)@h
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ori r0, r0, (cache_post_test_inst - cache_post_test6_reloc)@l
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add r13, r13, r0
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/* Copy the test instructions to the test area */
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lwz r0, 4(r13)
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stw r0, 0(r11)
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lwz r0, 8(r13)
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stw r0, 4(r11)
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sync
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/* Invalidate the cache line */
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icbi r0, r11
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sync
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isync
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/* Execute the test instructions */
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mtlr r11
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blrl
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/* Replace the test instruction */
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lwz r0, 0(r13)
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stw r0, 0(r11)
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sync
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/* Invalidate the cache line */
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icbi r0, r11
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sync
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isync
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/* Execute the test instructions */
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mtlr r11
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blrl
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mr r13, r3
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CACHE_POST_IINVALIDATE()
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CACHE_POST_DINVALIDATE()
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CACHE_POST_DISABLE()
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mr r3, r13
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mtlr r9
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blr
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/* Test instructions.
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*/
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cache_post_test_inst:
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li r3, 0
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li r3, -1
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blr
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#endif /* CONFIG_POST & CONFIG_SYS_POST_CACHE */
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