upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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674 lines
17 KiB
674 lines
17 KiB
/*
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* (C) Copyright 2000-2008
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <hwconfig.h>
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#include <mpc8xx.h>
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#ifdef CONFIG_PS2MULT
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#include <ps2mult.h>
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#endif
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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extern flash_info_t flash_info[]; /* FLASH chips info */
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DECLARE_GLOBAL_DATA_PTR;
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static long int dram_size (long int, long int *, long int);
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#define _NOT_USED_ 0xFFFFFFFF
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/* UPM initialization table for SDRAM: 40, 50, 66 MHz CLKOUT @ CAS latency 2, tWR=2 */
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const uint sdram_table[] =
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{
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/*
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* Single Read. (Offset 0 in UPMA RAM)
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*/
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0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
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0x1FF5FC47, /* last */
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/*
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* SDRAM Initialization (offset 5 in UPMA RAM)
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*
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* This is no UPM entry point. The following definition uses
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* the remaining space to establish an initialization
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* sequence, which is executed by a RUN command.
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*
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*/
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0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
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/*
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* Burst Read. (Offset 8 in UPMA RAM)
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*/
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0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
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0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Single Write. (Offset 18 in UPMA RAM)
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*/
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0x1F0DFC04, 0xEEABBC00, 0x11B77C04, 0xEFFAFC44,
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0x1FF5FC47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Burst Write. (Offset 20 in UPMA RAM)
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*/
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0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
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0xF0AFFC00, 0xF0AFFC04, 0xE1BAFC44, 0x1FF5FC47, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Refresh (Offset 30 in UPMA RAM)
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*/
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0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
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0xFFFFFC84, 0xFFFFFC07, /* last */
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_NOT_USED_, _NOT_USED_,
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_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
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/*
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* Exception. (Offset 3c in UPMA RAM)
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*/
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0xFFFFFC07, /* last */
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_NOT_USED_, _NOT_USED_, _NOT_USED_,
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};
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/* ------------------------------------------------------------------------- */
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/*
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* Check Board Identity:
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*
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* Test TQ ID string (TQM8xx...)
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* If present, check for "L" type (no second DRAM bank),
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* otherwise "L" type is assumed as default.
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*
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* Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
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*/
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int checkboard (void)
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{
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char buf[64];
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int i;
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int l = getenv_f("serial#", buf, sizeof(buf));
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puts ("Board: ");
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if (l < 0 || strncmp(buf, "TQM8", 4)) {
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puts ("### No HW ID - assuming TQM8xxL\n");
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return (0);
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}
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if ((buf[6] == 'L')) { /* a TQM8xxL type */
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gd->board_type = 'L';
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}
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if ((buf[6] == 'M')) { /* a TQM8xxM type */
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gd->board_type = 'M';
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}
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if ((buf[6] == 'D')) { /* a TQM885D type */
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gd->board_type = 'D';
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}
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for (i = 0; i < l; ++i) {
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if (buf[i] == ' ')
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break;
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putc (buf[i]);
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}
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putc ('\n');
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size8, size9, size10;
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long int size_b0 = 0;
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long int size_b1 = 0;
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upmconfig (UPMA, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
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/*
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* The following value is used as an address (i.e. opcode) for
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* the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
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* the port size is 32bit the SDRAM does NOT "see" the lower two
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* address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
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* MICRON SDRAMs:
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* -> 0 00 010 0 010
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* | | | | +- Burst Length = 4
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* | | | +----- Burst Type = Sequential
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* | | +------- CAS Latency = 2
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* | +----------- Operating Mode = Standard
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* +-------------- Write Burst Mode = Programmed Burst Length
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*/
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memctl->memc_mar = 0x00000088;
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/*
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* Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
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* preliminary addresses - these have to be modified after the
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* SDRAM size has been determined.
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*/
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memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
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memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
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#ifndef CONFIG_CAN_DRIVER
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if ((board_type != 'L') &&
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(board_type != 'M') &&
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(board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
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memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
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memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
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}
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#endif /* CONFIG_CAN_DRIVER */
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memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
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udelay (200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
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udelay (1);
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memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
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udelay (1);
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#ifndef CONFIG_CAN_DRIVER
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if ((board_type != 'L') &&
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(board_type != 'M') &&
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(board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
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memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
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udelay (1);
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memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
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udelay (1);
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}
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#endif /* CONFIG_CAN_DRIVER */
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memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
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udelay (1000);
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/*
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* Check Bank 0 Memory Size for re-configuration
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*
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* try 8 column mode
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*/
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size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
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debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
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udelay (1000);
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/*
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* try 9 column mode
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*/
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size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
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debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
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udelay(1000);
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#if defined(CONFIG_SYS_MAMR_10COL)
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/*
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* try 10 column mode
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*/
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size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
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debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
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#else
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size10 = 0;
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#endif /* CONFIG_SYS_MAMR_10COL */
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if ((size8 < size10) && (size9 < size10)) {
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size_b0 = size10;
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} else if ((size8 < size9) && (size10 < size9)) {
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size_b0 = size9;
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memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
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udelay (500);
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} else {
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size_b0 = size8;
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memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
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udelay (500);
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}
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debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
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#ifndef CONFIG_CAN_DRIVER
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if ((board_type != 'L') &&
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(board_type != 'M') &&
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(board_type != 'D') ) { /* only one SDRAM bank on L, M and D modules */
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/*
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* Check Bank 1 Memory Size
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* use current column settings
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* [9 column SDRAM may also be used in 8 column mode,
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* but then only half the real size will be used.]
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*/
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size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
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SDRAM_MAX_SIZE);
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debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
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} else {
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size_b1 = 0;
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}
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#endif /* CONFIG_CAN_DRIVER */
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udelay (1000);
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/*
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* Adjust refresh rate depending on SDRAM type, both banks
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* For types > 128 MBit leave it at the current (fast) rate
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*/
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if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
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/* reduce to 15.6 us (62.4 us / quad) */
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memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
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udelay (1000);
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}
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/*
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* Final mapping: map bigger bank first
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*/
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if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
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memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
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memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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if (size_b0 > 0) {
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/*
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* Position Bank 0 immediately above Bank 1
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*/
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memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
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memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
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+ size_b1;
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} else {
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unsigned long reg;
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/*
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* No bank 0
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*
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* invalidate bank
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*/
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memctl->memc_br2 = 0;
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/* adjust refresh rate depending on SDRAM type, one bank */
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reg = memctl->memc_mptpr;
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reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
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memctl->memc_mptpr = reg;
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}
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} else { /* SDRAM Bank 0 is bigger - map first */
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memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
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memctl->memc_br2 =
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(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
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if (size_b1 > 0) {
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/*
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* Position Bank 1 immediately above Bank 0
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*/
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memctl->memc_or3 =
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((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
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memctl->memc_br3 =
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((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
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+ size_b0;
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} else {
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unsigned long reg;
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#ifndef CONFIG_CAN_DRIVER
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/*
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* No bank 1
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*
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* invalidate bank
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*/
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memctl->memc_br3 = 0;
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#endif /* CONFIG_CAN_DRIVER */
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/* adjust refresh rate depending on SDRAM type, one bank */
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reg = memctl->memc_mptpr;
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reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
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memctl->memc_mptpr = reg;
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}
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}
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udelay (10000);
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#ifdef CONFIG_CAN_DRIVER
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/* UPM initialization for CAN @ CLKOUT <= 66 MHz */
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/* Initialize OR3 / BR3 */
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memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
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memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
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/* Initialize MBMR */
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memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
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/* Initialize UPMB for CAN: single read */
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memctl->memc_mdr = 0xFFFFCC04;
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memctl->memc_mcr = 0x0100 | UPMB;
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memctl->memc_mdr = 0x0FFFD004;
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memctl->memc_mcr = 0x0101 | UPMB;
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memctl->memc_mdr = 0x0FFFC000;
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memctl->memc_mcr = 0x0102 | UPMB;
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memctl->memc_mdr = 0x3FFFC004;
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memctl->memc_mcr = 0x0103 | UPMB;
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memctl->memc_mdr = 0xFFFFDC07;
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memctl->memc_mcr = 0x0104 | UPMB;
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/* Initialize UPMB for CAN: single write */
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memctl->memc_mdr = 0xFFFCCC04;
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memctl->memc_mcr = 0x0118 | UPMB;
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memctl->memc_mdr = 0xCFFCDC04;
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memctl->memc_mcr = 0x0119 | UPMB;
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memctl->memc_mdr = 0x3FFCC000;
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memctl->memc_mcr = 0x011A | UPMB;
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memctl->memc_mdr = 0xFFFCC004;
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memctl->memc_mcr = 0x011B | UPMB;
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memctl->memc_mdr = 0xFFFDC405;
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memctl->memc_mcr = 0x011C | UPMB;
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#endif /* CONFIG_CAN_DRIVER */
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#ifdef CONFIG_ISP1362_USB
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/* Initialize OR5 / BR5 */
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memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362;
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memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362;
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#endif /* CONFIG_ISP1362_USB */
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return (size_b0 + size_b1);
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}
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/* ------------------------------------------------------------------------- */
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/*
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* Check memory range for valid RAM. A simple memory test determines
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* the actually available RAM size between addresses `base' and
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* `base + maxsize'. Some (not all) hardware errors are detected:
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* - short between address lines
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* - short between data lines
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*/
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static long int dram_size (long int mamr_value, long int *base, long int maxsize)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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memctl->memc_mamr = mamr_value;
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return (get_ram_size(base, maxsize));
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}
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/* ------------------------------------------------------------------------- */
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#ifdef CONFIG_MISC_INIT_R
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extern void load_sernum_ethaddr(void);
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int misc_init_r (void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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load_sernum_ethaddr();
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#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
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int scy, trlx, flash_or_timing, clk_diff;
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scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
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if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
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trlx = OR_TRLX;
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scy *= 2;
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} else {
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trlx = 0;
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}
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/*
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* We assume that each 10MHz of bus clock require 1-clk SCY
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* adjustment.
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*/
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clk_diff = (gd->bus_clk / 1000000) - 50;
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/*
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* We need proper rounding here. This is what the "+5" and "-5"
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* are here for.
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*/
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if (clk_diff >= 0)
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scy += (clk_diff + 5) / 10;
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else
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scy += (clk_diff - 5) / 10;
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/*
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* For bus frequencies above 50MHz, we want to use relaxed timing
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* (OR_TRLX).
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*/
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if (gd->bus_clk >= 50000000)
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trlx = OR_TRLX;
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else
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trlx = 0;
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if (trlx)
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scy /= 2;
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if (scy > 0xf)
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scy = 0xf;
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if (scy < 1)
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scy = 1;
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flash_or_timing = (scy << 4) | trlx |
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(CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
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memctl->memc_or0 =
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flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
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#else
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memctl->memc_or0 =
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CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
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#endif
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memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
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|
|
|
debug ("## BR0: 0x%08x OR0: 0x%08x\n",
|
|
memctl->memc_br0, memctl->memc_or0);
|
|
|
|
if (flash_info[1].size) {
|
|
#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
|
|
memctl->memc_or1 = flash_or_timing |
|
|
(-flash_info[1].size & 0xFFFF8000);
|
|
#else
|
|
memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH |
|
|
(-flash_info[1].size & 0xFFFF8000);
|
|
#endif
|
|
memctl->memc_br1 =
|
|
((CONFIG_SYS_FLASH_BASE +
|
|
flash_info[0].
|
|
size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
|
|
|
|
debug ("## BR1: 0x%08x OR1: 0x%08x\n",
|
|
memctl->memc_br1, memctl->memc_or1);
|
|
} else {
|
|
memctl->memc_br1 = 0; /* invalidate bank */
|
|
|
|
debug ("## DISABLE BR1: 0x%08x OR1: 0x%08x\n",
|
|
memctl->memc_br1, memctl->memc_or1);
|
|
}
|
|
|
|
# ifdef CONFIG_IDE_LED
|
|
/* Configure PA15 as output port */
|
|
immap->im_ioport.iop_padir |= 0x0001;
|
|
immap->im_ioport.iop_paodr |= 0x0001;
|
|
immap->im_ioport.iop_papar &= ~0x0001;
|
|
immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */
|
|
# endif
|
|
|
|
return (0);
|
|
}
|
|
#endif /* CONFIG_MISC_INIT_R */
|
|
|
|
|
|
# ifdef CONFIG_IDE_LED
|
|
void ide_led (uchar led, uchar status)
|
|
{
|
|
volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
|
|
|
|
/* We have one led for both pcmcia slots */
|
|
if (status) { /* led on */
|
|
immap->im_ioport.iop_padat |= 0x0001;
|
|
} else {
|
|
immap->im_ioport.iop_padat &= ~0x0001;
|
|
}
|
|
}
|
|
# endif
|
|
|
|
#ifdef CONFIG_LCD_INFO
|
|
#include <lcd.h>
|
|
#include <version.h>
|
|
#include <timestamp.h>
|
|
|
|
void lcd_show_board_info(void)
|
|
{
|
|
char temp[32];
|
|
|
|
lcd_printf ("%s (%s - %s)\n", U_BOOT_VERSION, U_BOOT_DATE, U_BOOT_TIME);
|
|
lcd_printf ("(C) 2008 DENX Software Engineering GmbH\n");
|
|
lcd_printf (" Wolfgang DENK, wd@denx.de\n");
|
|
#ifdef CONFIG_LCD_INFO_BELOW_LOGO
|
|
lcd_printf ("MPC823 CPU at %s MHz\n",
|
|
strmhz(temp, gd->cpu_clk));
|
|
lcd_printf (" %ld MB RAM, %ld MB Flash\n",
|
|
gd->ram_size >> 20,
|
|
gd->bd->bi_flashsize >> 20 );
|
|
#else
|
|
/* leave one blank line */
|
|
lcd_printf ("\nMPC823 CPU at %s MHz, %ld MB RAM, %ld MB Flash\n",
|
|
strmhz(temp, gd->cpu_clk),
|
|
gd->ram_size >> 20,
|
|
gd->bd->bi_flashsize >> 20 );
|
|
#endif /* CONFIG_LCD_INFO_BELOW_LOGO */
|
|
}
|
|
#endif /* CONFIG_LCD_INFO */
|
|
|
|
/*
|
|
* Device Tree Support
|
|
*/
|
|
#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
|
|
int fdt_set_node_and_value (void *blob,
|
|
char *nodename,
|
|
char *regname,
|
|
void *var,
|
|
int size)
|
|
{
|
|
int ret = 0;
|
|
int nodeoffset = 0;
|
|
|
|
nodeoffset = fdt_path_offset (blob, nodename);
|
|
if (nodeoffset >= 0) {
|
|
ret = fdt_setprop (blob, nodeoffset, regname, var,
|
|
size);
|
|
if (ret < 0) {
|
|
printf("ft_blob_update(): "
|
|
"cannot set %s/%s property; err: %s\n",
|
|
nodename, regname, fdt_strerror (ret));
|
|
}
|
|
} else {
|
|
printf("ft_blob_update(): "
|
|
"cannot find %s node err:%s\n",
|
|
nodename, fdt_strerror (nodeoffset));
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
int fdt_del_node_name (void *blob, char *nodename)
|
|
{
|
|
int ret = 0;
|
|
int nodeoffset = 0;
|
|
|
|
nodeoffset = fdt_path_offset (blob, nodename);
|
|
if (nodeoffset >= 0) {
|
|
ret = fdt_del_node (blob, nodeoffset);
|
|
if (ret < 0) {
|
|
printf("%s: cannot delete %s; err: %s\n",
|
|
__func__, nodename, fdt_strerror (ret));
|
|
}
|
|
} else {
|
|
printf("%s: cannot find %s node err:%s\n",
|
|
__func__, nodename, fdt_strerror (nodeoffset));
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
int fdt_del_prop_name (void *blob, char *nodename, char *propname)
|
|
{
|
|
int ret = 0;
|
|
int nodeoffset = 0;
|
|
|
|
nodeoffset = fdt_path_offset (blob, nodename);
|
|
if (nodeoffset >= 0) {
|
|
ret = fdt_delprop (blob, nodeoffset, propname);
|
|
if (ret < 0) {
|
|
printf("%s: cannot delete %s %s; err: %s\n",
|
|
__func__, nodename, propname,
|
|
fdt_strerror (ret));
|
|
}
|
|
} else {
|
|
printf("%s: cannot find %s node err:%s\n",
|
|
__func__, nodename, fdt_strerror (nodeoffset));
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* update "brg" property in the blob
|
|
*/
|
|
void ft_blob_update (void *blob, bd_t *bd)
|
|
{
|
|
uchar enetaddr[6];
|
|
ulong brg_data = 0;
|
|
|
|
/* BRG */
|
|
brg_data = cpu_to_be32(bd->bi_busfreq);
|
|
fdt_set_node_and_value(blob,
|
|
"/soc/cpm", "brg-frequency",
|
|
&brg_data, sizeof(brg_data));
|
|
|
|
/* MAC addr */
|
|
if (eth_getenv_enetaddr("ethaddr", enetaddr)) {
|
|
fdt_set_node_and_value(blob,
|
|
"ethernet0", "local-mac-address",
|
|
enetaddr, sizeof(u8) * 6);
|
|
}
|
|
|
|
if (hwconfig_arg_cmp("fec", "off")) {
|
|
/* no FEC on this plattform, delete DTS nodes */
|
|
fdt_del_node_name (blob, "ethernet1");
|
|
fdt_del_node_name (blob, "mdio1");
|
|
/* also the aliases entries */
|
|
fdt_del_prop_name (blob, "/aliases", "ethernet1");
|
|
fdt_del_prop_name (blob, "/aliases", "mdio1");
|
|
} else {
|
|
/* adjust local-mac-address for FEC ethernet */
|
|
if (eth_getenv_enetaddr("eth1addr", enetaddr)) {
|
|
fdt_set_node_and_value(blob,
|
|
"ethernet1", "local-mac-address",
|
|
enetaddr, sizeof(u8) * 6);
|
|
}
|
|
}
|
|
}
|
|
|
|
int ft_board_setup(void *blob, bd_t *bd)
|
|
{
|
|
ft_cpu_setup(blob, bd);
|
|
ft_blob_update(blob, bd);
|
|
|
|
return 0;
|
|
}
|
|
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
|
|
|