upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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451 lines
12 KiB
451 lines
12 KiB
/*
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* Machine Specific Values for SMDK5250 board based on S5PC520
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*
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* Copyright (C) 2012 Samsung Electronics
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _SMDK5250_SETUP_H
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#define _SMDK5250_SETUP_H
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#include <config.h>
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#include <version.h>
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#include <asm/arch/cpu.h>
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/* GPIO Offsets for UART: GPIO Contol Register */
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#define EXYNOS5_GPIO_A0_CON_OFFSET 0x0
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#define EXYNOS5_GPIO_A1_CON_OFFSET 0x20
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/* TZPC : Register Offsets */
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#define TZPC0_BASE 0x10100000
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#define TZPC1_BASE 0x10110000
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#define TZPC2_BASE 0x10120000
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#define TZPC3_BASE 0x10130000
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#define TZPC4_BASE 0x10140000
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#define TZPC5_BASE 0x10150000
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#define TZPC6_BASE 0x10160000
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#define TZPC7_BASE 0x10170000
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#define TZPC8_BASE 0x10180000
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#define TZPC9_BASE 0x10190000
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/* CLK_SRC_CPU */
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/* 0 = MOUTAPLL, 1 = SCLKMPLL */
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#define MUX_HPM_SEL 0
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#define MUX_CPU_SEL 0
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#define MUX_APLL_SEL 1
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#define CLK_SRC_CPU_VAL ((MUX_HPM_SEL << 20) \
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| (MUX_CPU_SEL << 16) \
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| (MUX_APLL_SEL))
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/* CLK_DIV_CPU0 */
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#define ARM2_RATIO 0x0
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#define APLL_RATIO 0x1
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#define PCLK_DBG_RATIO 0x1
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#define ATB_RATIO 0x4
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#define PERIPH_RATIO 0x7
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#define ACP_RATIO 0x7
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#define CPUD_RATIO 0x2
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#define ARM_RATIO 0x0
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#define CLK_DIV_CPU0_VAL ((ARM2_RATIO << 28) \
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| (APLL_RATIO << 24) \
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| (PCLK_DBG_RATIO << 20) \
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| (ATB_RATIO << 16) \
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| (PERIPH_RATIO << 12) \
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| (ACP_RATIO << 8) \
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| (CPUD_RATIO << 4) \
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| (ARM_RATIO))
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/* CLK_DIV_CPU1 */
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#define HPM_RATIO 0x4
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#define COPY_RATIO 0x0
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#define CLK_DIV_CPU1_VAL ((HPM_RATIO << 4) \
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| (COPY_RATIO))
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#define APLL_MDIV 0x7D
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#define APLL_PDIV 0x3
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#define APLL_SDIV 0x0
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#define MPLL_MDIV 0x64
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#define MPLL_PDIV 0x3
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#define MPLL_SDIV 0x0
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#define CPLL_MDIV 0x96
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#define CPLL_PDIV 0x4
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#define CPLL_SDIV 0x0
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/* APLL_CON1 */
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#define APLL_CON1_VAL (0x00203800)
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/* MPLL_CON1 */
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#define MPLL_CON1_VAL (0x00203800)
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/* CPLL_CON1 */
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#define CPLL_CON1_VAL (0x00203800)
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#define EPLL_MDIV 0x60
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#define EPLL_PDIV 0x3
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#define EPLL_SDIV 0x3
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#define EPLL_CON1_VAL 0x00000000
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#define EPLL_CON2_VAL 0x00000080
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#define VPLL_MDIV 0x96
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#define VPLL_PDIV 0x3
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#define VPLL_SDIV 0x2
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#define VPLL_CON1_VAL 0x00000000
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#define VPLL_CON2_VAL 0x00000080
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#define BPLL_MDIV 0x215
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#define BPLL_PDIV 0xC
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#define BPLL_SDIV 0x1
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#define BPLL_CON1_VAL 0x00203800
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/* Set PLL */
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#define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv)
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#define APLL_CON0_VAL set_pll(APLL_MDIV, APLL_PDIV, APLL_SDIV)
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#define MPLL_CON0_VAL set_pll(MPLL_MDIV, MPLL_PDIV, MPLL_SDIV)
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#define CPLL_CON0_VAL set_pll(CPLL_MDIV, CPLL_PDIV, CPLL_SDIV)
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#define EPLL_CON0_VAL set_pll(EPLL_MDIV, EPLL_PDIV, EPLL_SDIV)
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#define VPLL_CON0_VAL set_pll(VPLL_MDIV, VPLL_PDIV, VPLL_SDIV)
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#define BPLL_CON0_VAL set_pll(BPLL_MDIV, BPLL_PDIV, BPLL_SDIV)
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/* CLK_SRC_CORE0 */
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#define CLK_SRC_CORE0_VAL 0x00060000
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/* CLK_SRC_CORE1 */
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#define CLK_SRC_CORE1_VAL 0x100
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/* CLK_DIV_CORE0 */
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#define CLK_DIV_CORE0_VAL 0x120000
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/* CLK_DIV_CORE1 */
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#define CLK_DIV_CORE1_VAL 0x07070700
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/* CLK_SRC_CDREX */
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#define CLK_SRC_CDREX_INIT_VAL 0x1
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#define CLK_SRC_CDREX_VAL 0x111
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/* CLK_DIV_CDREX */
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#define CLK_DIV_CDREX_INIT_VAL 0x71771111
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#define MCLK_CDREX2_RATIO 0x0
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#define ACLK_EFCON_RATIO 0x1
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#define MCLK_DPHY_RATIO 0x0
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#define MCLK_CDREX_RATIO 0x0
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#define ACLK_C2C_200_RATIO 0x1
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#define C2C_CLK_400_RATIO 0x1
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#define PCLK_CDREX_RATIO 0x3
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#define ACLK_CDREX_RATIO 0x1
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#define CLK_DIV_CDREX_VAL ((MCLK_DPHY_RATIO << 20) \
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| (MCLK_CDREX_RATIO << 16) \
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| (ACLK_C2C_200_RATIO << 12) \
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| (C2C_CLK_400_RATIO << 8) \
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| (PCLK_CDREX_RATIO << 4) \
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| (ACLK_CDREX_RATIO))
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#define MCLK_EFPHY_RATIO 0x4
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#define CLK_DIV_CDREX2_VAL MCLK_EFPHY_RATIO
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/* CLK_DIV_ACP */
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#define CLK_DIV_ACP_VAL 0x12
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/* CLK_SRC_TOP0 */
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#define MUX_ACLK_300_GSCL_SEL 0x1
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#define MUX_ACLK_300_GSCL_MID_SEL 0x0
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#define MUX_ACLK_400_SEL 0x0
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#define MUX_ACLK_333_SEL 0x0
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#define MUX_ACLK_300_DISP1_SEL 0x1
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#define MUX_ACLK_300_DISP1_MID_SEL 0x0
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#define MUX_ACLK_200_SEL 0x0
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#define MUX_ACLK_166_SEL 0x0
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#define CLK_SRC_TOP0_VAL ((MUX_ACLK_300_GSCL_SEL << 25) \
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| (MUX_ACLK_300_GSCL_MID_SEL << 24) \
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| (MUX_ACLK_400_SEL << 20) \
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| (MUX_ACLK_333_SEL << 16) \
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| (MUX_ACLK_300_DISP1_SEL << 15) \
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| (MUX_ACLK_300_DISP1_MID_SEL << 14) \
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| (MUX_ACLK_200_SEL << 12) \
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| (MUX_ACLK_166_SEL << 8))
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/* CLK_SRC_TOP1 */
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#define MUX_ACLK_400_ISP_SEL 0x0
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#define MUX_ACLK_400_IOP_SEL 0x0
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#define MUX_ACLK_MIPI_HSI_TXBASE_SEL 0x0
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#define CLK_SRC_TOP1_VAL ((MUX_ACLK_400_ISP_SEL << 24) \
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|(MUX_ACLK_400_IOP_SEL << 20) \
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|(MUX_ACLK_MIPI_HSI_TXBASE_SEL << 16))
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/* CLK_SRC_TOP2 */
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#define MUX_BPLL_USER_SEL 0x1
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#define MUX_MPLL_USER_SEL 0x1
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#define MUX_VPLL_SEL 0x0
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#define MUX_EPLL_SEL 0x0
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#define MUX_CPLL_SEL 0x0
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#define VPLLSRC_SEL 0x0
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#define CLK_SRC_TOP2_VAL ((MUX_BPLL_USER_SEL << 24) \
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| (MUX_MPLL_USER_SEL << 20) \
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| (MUX_VPLL_SEL << 16) \
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| (MUX_EPLL_SEL << 12) \
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| (MUX_CPLL_SEL << 8) \
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| (VPLLSRC_SEL))
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/* CLK_SRC_TOP3 */
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#define MUX_ACLK_333_SUB_SEL 0x1
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#define MUX_ACLK_400_SUB_SEL 0x1
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#define MUX_ACLK_266_ISP_SUB_SEL 0x1
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#define MUX_ACLK_266_GPS_SUB_SEL 0x1
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#define MUX_ACLK_300_GSCL_SUB_SEL 0x1
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#define MUX_ACLK_266_GSCL_SUB_SEL 0x1
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#define MUX_ACLK_300_DISP1_SUB_SEL 0x1
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#define MUX_ACLK_200_DISP1_SUB_SEL 0x1
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#define CLK_SRC_TOP3_VAL ((MUX_ACLK_333_SUB_SEL << 24) \
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| (MUX_ACLK_400_SUB_SEL << 20) \
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| (MUX_ACLK_266_ISP_SUB_SEL << 16) \
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| (MUX_ACLK_266_GPS_SUB_SEL << 12) \
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| (MUX_ACLK_300_GSCL_SUB_SEL << 10) \
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| (MUX_ACLK_266_GSCL_SUB_SEL << 8) \
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| (MUX_ACLK_300_DISP1_SUB_SEL << 6) \
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| (MUX_ACLK_200_DISP1_SUB_SEL << 4))
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/* CLK_DIV_TOP0 */
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#define ACLK_300_RATIO 0x0
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#define ACLK_400_RATIO 0x3
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#define ACLK_333_RATIO 0x2
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#define ACLK_266_RATIO 0x2
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#define ACLK_200_RATIO 0x3
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#define ACLK_166_RATIO 0x5
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#define ACLK_133_RATIO 0x1
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#define ACLK_66_RATIO 0x5
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#define CLK_DIV_TOP0_VAL ((ACLK_300_RATIO << 28) \
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| (ACLK_400_RATIO << 24) \
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| (ACLK_333_RATIO << 20) \
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| (ACLK_266_RATIO << 16) \
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| (ACLK_200_RATIO << 12) \
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| (ACLK_166_RATIO << 8) \
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| (ACLK_133_RATIO << 4) \
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| (ACLK_66_RATIO))
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/* CLK_DIV_TOP1 */
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#define ACLK_MIPI_HSI_TX_BASE_RATIO 0x3
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#define ACLK_66_PRE_RATIO 0x1
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#define ACLK_400_ISP_RATIO 0x1
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#define ACLK_400_IOP_RATIO 0x1
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#define ACLK_300_GSCL_RATIO 0x0
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#define ACLK_266_GPS_RATIO 0x7
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#define CLK_DIV_TOP1_VAL ((ACLK_MIPI_HSI_TX_BASE_RATIO << 28) \
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| (ACLK_66_PRE_RATIO << 24) \
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| (ACLK_400_ISP_RATIO << 20) \
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| (ACLK_400_IOP_RATIO << 16) \
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| (ACLK_300_GSCL_RATIO << 12) \
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| (ACLK_266_GPS_RATIO << 8))
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/* APLL_LOCK */
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#define APLL_LOCK_VAL (0x3E8)
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/* MPLL_LOCK */
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#define MPLL_LOCK_VAL (0x2F1)
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/* CPLL_LOCK */
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#define CPLL_LOCK_VAL (0x3E8)
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/* EPLL_LOCK */
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#define EPLL_LOCK_VAL (0x2321)
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/* VPLL_LOCK */
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#define VPLL_LOCK_VAL (0x2321)
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/* BPLL_LOCK */
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#define BPLL_LOCK_VAL (0x3E8)
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/* CLK_SRC_PERIC0 */
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/* SRC_CLOCK = SCLK_MPLL */
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#define PWM_SEL 0
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#define UART4_SEL 6
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#define UART3_SEL 6
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#define UART2_SEL 6
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#define UART1_SEL 6
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#define UART0_SEL 6
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#define CLK_SRC_PERIC0_VAL ((PWM_SEL << 24) \
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| (UART4_SEL << 16) \
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| (UART3_SEL << 12) \
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| (UART2_SEL << 8) \
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| (UART1_SEL << 4) \
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| (UART0_SEL << 0))
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#define CLK_SRC_FSYS_VAL 0x66666
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#define CLK_DIV_FSYS0_VAL 0x0BB00000
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#define CLK_DIV_FSYS1_VAL 0x000f000f
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#define CLK_DIV_FSYS2_VAL 0x020f020f
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#define CLK_DIV_FSYS3_VAL 0x000f
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/* CLK_DIV_PERIC0 */
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#define UART5_RATIO 8
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#define UART4_RATIO 8
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#define UART3_RATIO 8
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#define UART2_RATIO 8
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#define UART1_RATIO 8
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#define UART0_RATIO 8
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#define CLK_DIV_PERIC0_VAL ((UART4_RATIO << 16) \
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| (UART3_RATIO << 12) \
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| (UART2_RATIO << 8) \
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| (UART1_RATIO << 4) \
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| (UART0_RATIO << 0))
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/* CLK_DIV_PERIC3 */
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#define PWM_RATIO 8
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#define CLK_DIV_PERIC3_VAL (PWM_RATIO << 0)
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/* CLK_SRC_LEX */
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#define CLK_SRC_LEX_VAL 0x0
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/* CLK_DIV_LEX */
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#define CLK_DIV_LEX_VAL 0x10
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/* CLK_DIV_R0X */
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#define CLK_DIV_R0X_VAL 0x10
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/* CLK_DIV_L0X */
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#define CLK_DIV_R1X_VAL 0x10
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/* SCLK_SRC_ISP */
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#define SCLK_SRC_ISP_VAL 0x600
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/* CLK_DIV_ISP0 */
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#define CLK_DIV_ISP0_VAL 0x31
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/* CLK_DIV_ISP1 */
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#define CLK_DIV_ISP1_VAL 0x0
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/* CLK_DIV_ISP2 */
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#define CLK_DIV_ISP2_VAL 0x1
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#define MPLL_DEC (MPLL_MDIV * MPLL_MDIV / (MPLL_PDIV * 2^(MPLL_SDIV-1)))
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/*
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* TZPC Register Value :
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* R0SIZE: 0x0 : Size of secured ram
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*/
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#define R0SIZE 0x0
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/*
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* TZPC Decode Protection Register Value :
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* DECPROTXSET: 0xFF : Set Decode region to non-secure
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*/
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#define DECPROTXSET 0xFF
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/* DMC Init */
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#define SET 1
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#define RESET 0
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/* (Memory Interleaving Size = 1 << IV_SIZE) */
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#define CONFIG_IV_SIZE 0x07
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#define PHY_RESET_VAL (0 << 0)
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/*ZQ Configurations */
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#define PHY_CON16_RESET_VAL 0x08000304
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#define ZQ_MODE_DDS_VAL (0x5 << 24)
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#define ZQ_MODE_TERM_VAL (0x5 << 21)
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#define SET_ZQ_MODE_DDS_VAL(x) (x = (x & ~(0x7 << 24)) | ZQ_MODE_DDS_VAL)
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#define SET_ZQ_MODE_TERM_VAL(x) (x = (x & ~(0x7 << 21)) | ZQ_MODE_TERM_VAL)
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#define ZQ_MODE_NOTERM (1 << 19)
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#define ZQ_CLK_DIV_EN (1 << 18)
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#define ZQ_MANUAL_STR (1 << 1)
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/* Channel and Chip Selection */
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#define CONFIG_DMC_CHANNELS 2
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#define CONFIG_CHIPS_PER_CHANNEL 2
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#define SET_CMD_CHANNEL(x, y) (x = (x & ~(1 << 28)) | y << 28)
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#define SET_CMD_CHIP(x, y) (x = (x & ~(1 << 20)) | y << 20)
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/* Diret Command */
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#define DIRECT_CMD_NOP 0x07000000
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#define DIRECT_CMD_MRS1 0x00071C00
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#define DIRECT_CMD_MRS2 0x00010BFC
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#define DIRECT_CMD_MRS3 0x00000708
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#define DIRECT_CMD_MRS4 0x00000818
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#define DIRECT_CMD_PALL 0x01000000
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/* DLL Resync */
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#define FP_RSYNC (1 << 3)
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#define CONFIG_CTRL_DLL_ON(x, y) (x = (x & ~(1 << 5)) | y << 5)
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#define CONFIG_CTRL_START(x, y) (x = (x & ~(1 << 6)) | y << 6)
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#define SET_CTRL_FORCE_VAL(x, y) (x = (x & ~(0x7F << 8)) | y << 8)
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/* RDLVL */
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#define PHY_CON0_RESET_VAL 0x17023240
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#define DDR_MODE_LPDDR2 0x2
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#define BYTE_RDLVL_EN (1 << 13)
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#define CTRL_ATGATE (1 << 6)
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#define SET_CTRL_DDR_MODE(x, y) (x = (x & ~(0x3 << 11)) | y << 11)
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#define PHY_CON1_RESET_VAL 0x9210100
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#define RDLVL_RDDATAPADJ 0x1
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#define SET_RDLVL_RDDATAPADJ ((PHY_CON1_RESET_VAL & ~(0xFFFF << 0))\
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| RDLVL_RDDATAPADJ << 0)
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#define PHY_CON2_RESET_VAL 0x00010004
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#define RDLVL_EN (1 << 25)
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#define RDDSKEW_CLEAR (1 << 13)
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#define CTRL_RDLVL_DATA_EN (1 << 1)
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#define LPDDR2_ADDR 0x00000208
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#define DMC_MEMCONFIG0_VAL 0x00001323
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#define DMC_MEMCONFIG1_VAL 0x00001323
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#define DMC_MEMBASECONFIG0_VAL 0x00400780
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#define DMC_MEMBASECONFIG1_VAL 0x00800780
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#define DMC_MEMCONTROL_VAL 0x00212500
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#define DMC_PRECHCONFIG_VAL 0xFF000000
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#define DMC_PWRDNCONFIG_VAL 0xFFFF00FF
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#define DMC_TIMINGREF_VAL 0x0000005D
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#define DMC_TIMINGROW_VAL 0x2336544C
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#define DMC_TIMINGDATA_VAL 0x24202408
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#define DMC_TIMINGPOWER_VAL 0x38260235
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#define CTRL_BSTLEN 0x04
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#define CTRL_RDLAT 0x08
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#define PHY_CON42_VAL (CTRL_BSTLEN << 8 | CTRL_RDLAT << 0)
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/* DQS, DQ, DEBUG offsets */
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#define SET_DQS_OFFSET_VAL 0x7F7F7F7F
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#define SET_DQ_OFFSET_VAL 0x7F7F7F7F
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#define SET_DEBUG_OFFSET_VAL 0x7F
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#define RESET_DQS_OFFSET_VAL 0x08080808
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#define RESET_DQ_OFFSET_VAL 0x08080808
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#define RESET_DEBUG_OFFSET_VAL 0x8
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#define CTRL_PULLD_DQ (0x0F << 8)
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#define CTRL_PULLD_DQS (0x0F << 0)
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#define DFI_INIT_START (1 << 28)
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#define CLK_STOP_EN (1 << 0)
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#define DPWRDN_EN (1 << 1)
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#define DSREF_EN (1 << 5)
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#define AREF_EN (1 << 5)
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void sdelay(unsigned long);
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void mem_ctrl_init(void);
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void system_clock_init(void);
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void tzpc_init(void);
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#endif
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