upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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70 lines
1.0 KiB
70 lines
1.0 KiB
/*
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* (C) Copyright 2011
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_CLOCK_H
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#define __ASM_ARCH_CLOCK_H
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#include <common.h>
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#ifdef CONFIG_MX35_HCLK_FREQ
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#define MXC_HCLK CONFIG_MX35_HCLK_FREQ
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#else
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#define MXC_HCLK 24000000
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#endif
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#ifdef CONFIG_MX35_CLK32
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#define MXC_CLK32 CONFIG_MX35_CLK32
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#else
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#define MXC_CLK32 32768
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#endif
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enum mxc_clock {
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MXC_ARM_CLK,
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MXC_AHB_CLK,
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MXC_IPG_CLK,
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MXC_IPG_PERCLK,
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MXC_UART_CLK,
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MXC_ESDHC1_CLK,
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MXC_ESDHC2_CLK,
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MXC_ESDHC3_CLK,
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MXC_USB_CLK,
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MXC_CSPI_CLK,
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MXC_FEC_CLK,
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MXC_I2C_CLK,
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};
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enum mxc_main_clock {
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CPU_CLK,
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AHB_CLK,
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IPG_CLK,
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IPG_PER_CLK,
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NFC_CLK,
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USB_CLK,
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HSP_CLK,
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};
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enum mxc_peri_clock {
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UART1_BAUD,
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UART2_BAUD,
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UART3_BAUD,
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SSI1_BAUD,
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SSI2_BAUD,
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CSI_BAUD,
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MSHC_CLK,
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ESDHC1_CLK,
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ESDHC2_CLK,
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ESDHC3_CLK,
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SPDIF_CLK,
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SPI1_CLK,
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SPI2_CLK,
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};
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u32 imx_get_uartclk(void);
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u32 imx_get_fecclk(void);
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unsigned int mxc_get_clock(enum mxc_clock clk);
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#endif /* __ASM_ARCH_CLOCK_H */
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