upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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148 lines
5.0 KiB
148 lines
5.0 KiB
/*
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* (C) Copyright 2007 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Based on Xilinx drivers
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*
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*/
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typedef struct {
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u32 regbaseaddress; /* Base address of registers */
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u32 databaseaddress; /* Base address of data for FIFOs */
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} xpacketfifov100b;
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typedef struct {
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u32 baseaddress; /* Base address (of IPIF) */
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u32 isstarted; /* Device is currently started 0-no, 1-yes */
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xpacketfifov100b recvfifo; /* FIFO used to receive frames */
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xpacketfifov100b sendfifo; /* FIFO used to send frames */
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} xemac;
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#define XIIF_V123B_IISR_OFFSET 32UL /* IP interrupt status register */
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#define XIIF_V123B_RESET_MASK 0xAUL
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#define XIIF_V123B_RESETR_OFFSET 64UL /* reset register */
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/* This constant is used with the Reset Register */
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#define XPF_RESET_FIFO_MASK 0x0000000A
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#define XPF_COUNT_STATUS_REG_OFFSET 4UL
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/* These constants are used with the Occupancy/Vacancy Count Register. This
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* register also contains FIFO status */
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#define XPF_COUNT_MASK 0x0000FFFF
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#define XPF_DEADLOCK_MASK 0x20000000
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/* Offset of the MAC registers from the IPIF base address */
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#define XEM_REG_OFFSET 0x1100UL
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/*
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* Register offsets for the Ethernet MAC. Each register is 32 bits.
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*/
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#define XEM_ECR_OFFSET (XEM_REG_OFFSET + 0x4) /* MAC Control */
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#define XEM_SAH_OFFSET (XEM_REG_OFFSET + 0xC) /* Station addr, high */
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#define XEM_SAL_OFFSET (XEM_REG_OFFSET + 0x10) /* Station addr, low */
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#define XEM_RPLR_OFFSET (XEM_REG_OFFSET + 0x1C) /* Rx packet length */
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#define XEM_TPLR_OFFSET (XEM_REG_OFFSET + 0x20) /* Tx packet length */
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#define XEM_TSR_OFFSET (XEM_REG_OFFSET + 0x24) /* Tx status */
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#define XEM_PFIFO_OFFSET 0x2000UL
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/* Tx registers */
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#define XEM_PFIFO_TXREG_OFFSET (XEM_PFIFO_OFFSET + 0x0)
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/* Rx registers */
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#define XEM_PFIFO_RXREG_OFFSET (XEM_PFIFO_OFFSET + 0x10)
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/* Tx keyhole */
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#define XEM_PFIFO_TXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x100)
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/* Rx keyhole */
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#define XEM_PFIFO_RXDATA_OFFSET (XEM_PFIFO_OFFSET + 0x200)
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/*
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* EMAC Interrupt Registers (Status and Enable) masks. These registers are
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* part of the IPIF IP Interrupt registers
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*/
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/* A mask for all transmit interrupts, used in polled mode */
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#define XEM_EIR_XMIT_ALL_MASK (XEM_EIR_XMIT_DONE_MASK |\
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XEM_EIR_XMIT_ERROR_MASK | \
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XEM_EIR_XMIT_SFIFO_EMPTY_MASK |\
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XEM_EIR_XMIT_LFIFO_FULL_MASK)
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/* Xmit complete */
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#define XEM_EIR_XMIT_DONE_MASK 0x00000001UL
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/* Recv complete */
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#define XEM_EIR_RECV_DONE_MASK 0x00000002UL
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/* Xmit error */
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#define XEM_EIR_XMIT_ERROR_MASK 0x00000004UL
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/* Recv error */
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#define XEM_EIR_RECV_ERROR_MASK 0x00000008UL
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/* Xmit status fifo empty */
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#define XEM_EIR_XMIT_SFIFO_EMPTY_MASK 0x00000010UL
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/* Recv length fifo empty */
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#define XEM_EIR_RECV_LFIFO_EMPTY_MASK 0x00000020UL
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/* Xmit length fifo full */
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#define XEM_EIR_XMIT_LFIFO_FULL_MASK 0x00000040UL
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/* Recv length fifo overrun */
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#define XEM_EIR_RECV_LFIFO_OVER_MASK 0x00000080UL
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/* Recv length fifo underrun */
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#define XEM_EIR_RECV_LFIFO_UNDER_MASK 0x00000100UL
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/* Xmit status fifo overrun */
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#define XEM_EIR_XMIT_SFIFO_OVER_MASK 0x00000200UL
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/* Transmit status fifo underrun */
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#define XEM_EIR_XMIT_SFIFO_UNDER_MASK 0x00000400UL
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/* Transmit length fifo overrun */
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#define XEM_EIR_XMIT_LFIFO_OVER_MASK 0x00000800UL
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/* Transmit length fifo underrun */
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#define XEM_EIR_XMIT_LFIFO_UNDER_MASK 0x00001000UL
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/* Transmit pause pkt received */
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#define XEM_EIR_XMIT_PAUSE_MASK 0x00002000UL
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/*
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* EMAC Control Register (ECR)
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*/
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/* Full duplex mode */
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#define XEM_ECR_FULL_DUPLEX_MASK 0x80000000UL
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/* Reset transmitter */
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#define XEM_ECR_XMIT_RESET_MASK 0x40000000UL
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/* Enable transmitter */
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#define XEM_ECR_XMIT_ENABLE_MASK 0x20000000UL
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/* Reset receiver */
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#define XEM_ECR_RECV_RESET_MASK 0x10000000UL
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/* Enable receiver */
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#define XEM_ECR_RECV_ENABLE_MASK 0x08000000UL
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/* Enable PHY */
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#define XEM_ECR_PHY_ENABLE_MASK 0x04000000UL
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/* Enable xmit pad insert */
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#define XEM_ECR_XMIT_PAD_ENABLE_MASK 0x02000000UL
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/* Enable xmit FCS insert */
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#define XEM_ECR_XMIT_FCS_ENABLE_MASK 0x01000000UL
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/* Enable unicast addr */
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#define XEM_ECR_UNICAST_ENABLE_MASK 0x00020000UL
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/* Enable broadcast addr */
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#define XEM_ECR_BROAD_ENABLE_MASK 0x00008000UL
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/*
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* Transmit Status Register (TSR)
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*/
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/* Transmit excess deferral */
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#define XEM_TSR_EXCESS_DEFERRAL_MASK 0x80000000UL
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/* Transmit late collision */
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#define XEM_TSR_LATE_COLLISION_MASK 0x01000000UL
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