upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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440 lines
12 KiB
440 lines
12 KiB
/*
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* (C) Copyright 2003
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* Martin Winistoerfer, martinwinistoerfer@gmx.ch.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation,
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*/
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/*
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* File: 5xx_immap.h
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*
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* Discription: MPC555 Internal Memory Map
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*
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*/
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#ifndef __IMMAP_5XX__
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#define __IMMAP_5XX__
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/* System Configuration Registers.
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*/
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typedef struct sys_conf {
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uint sc_siumcr;
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uint sc_sypcr;
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char res1[6];
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ushort sc_swsr;
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uint sc_sipend;
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uint sc_simask;
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uint sc_siel;
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uint sc_sivec;
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uint sc_tesr;
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uint sc_sgpiodt1;
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uint sc_sgpiodt2;
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uint sc_sgpiocr;
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uint sc_emcr;
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uint sc_res1aa;
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uint sc_res1ab;
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uint sc_pdmcr;
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char res3[192];
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} sysconf5xx_t;
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/* Memory Controller Registers.
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*/
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typedef struct mem_ctlr {
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uint memc_br0;
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uint memc_or0;
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uint memc_br1;
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uint memc_or1;
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uint memc_br2;
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uint memc_or2;
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uint memc_br3;
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uint memc_or3;
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char res1[32];
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uint memc_dmbr;
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uint memc_dmor;
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char res2[48];
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ushort memc_mstat;
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ushort memc_res4a;
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char res3[132];
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} memctl5xx_t;
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/* System Integration Timers.
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*/
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typedef struct sys_int_timers {
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ushort sit_tbscr;
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char res1[2];
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uint sit_tbref0;
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uint sit_tbref1;
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char res2[20];
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ushort sit_rtcsc;
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char res3[2];
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uint sit_rtc;
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uint sit_rtsec;
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uint sit_rtcal;
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char res4[16];
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ushort sit_piscr;
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char res5[2];
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uint sit_pitc;
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uint sit_pitr;
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char res6[52];
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} sit5xx_t;
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/* Clocks and Reset
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*/
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typedef struct clk_and_reset {
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uint car_sccr;
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uint car_plprcr;
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ushort car_rsr;
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ushort car_res7a;
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ushort car_colir;
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ushort car_res7b;
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ushort car_vsrmcr;
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ushort car_res7c;
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char res1[108];
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} car5xx_t;
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#define TBSCR_TBE ((ushort)0x0001)
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/* System Integration Timer Keys
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*/
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typedef struct sitk {
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uint sitk_tbscrk;
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uint sitk_tbref0k;
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uint sitk_tbref1k;
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uint sitk_tbk;
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char res1[16];
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uint sitk_rtcsck;
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uint sitk_rtck;
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uint sitk_rtseck;
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uint sitk_rtcalk;
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char res2[16];
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uint sitk_piscrk;
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uint sitk_pitck;
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char res3[56];
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} sitk5xx_t;
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/* Clocks and Reset Keys.
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*/
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typedef struct cark {
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uint cark_sccrk;
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uint cark_plprcrk;
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uint cark_rsrk;
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char res1[1140];
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} cark8xx_t;
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/* The key to unlock registers maintained by keep-alive power.
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*/
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#define KAPWR_KEY ((unsigned int)0x55ccaa33)
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/* Flash Configuration
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*/
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typedef struct fl {
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uint fl_cmfmcr;
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uint fl_cmftst;
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uint fl_cmfctl;
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char res1[52];
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} fl5xx_t;
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/* Dpram Control
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*/
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typedef struct dprc {
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ushort dprc_dptmcr;
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ushort dprc_ramtst;
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ushort dprc_rambar;
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ushort dprc_misrh;
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ushort dprc_misrl;
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ushort dprc_miscnt;
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} dprc5xx_t;
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/* Time Processor Unit
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*/
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typedef struct tpu {
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ushort tpu_tpumcr;
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ushort tpu_tcr;
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ushort tpu_dscr;
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ushort tpu_dssr;
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ushort tpu_ticr;
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ushort tpu_cier;
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ushort tpu_cfsr0;
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ushort tpu_cfsr1;
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ushort tpu_cfsr2;
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ushort tpu_cfsr3;
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ushort tpu_hsqr0;
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ushort tpu_hsqr1;
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ushort tpu_hsrr0;
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ushort tpu_hsrr1;
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ushort tpu_cpr0;
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ushort tpu_cpr1;
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ushort tpu_cisr;
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ushort tpu_lr;
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ushort tpu_sglr;
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ushort tpu_dcnr;
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ushort tpu_tpumcr2;
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ushort tpu_tpumcr3;
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ushort tpu_isdr;
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ushort tpu_iscr;
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char res1[208];
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char tpu[16][16];
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char res2[512];
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} tpu5xx_t;
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/* QADC
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*/
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typedef struct qadc {
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ushort qadc_64mcr;
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ushort qadc_64test;
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ushort qadc_64int;
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u_char qadc_portqa;
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u_char qadc_portqb;
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ushort qadc_ddrqa;
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ushort qadc_qacr0;
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ushort qadc_qacr1;
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ushort qadc_qacr2;
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ushort qadc_qasr0;
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ushort qadc_qasr1;
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char res1[492];
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/* command convertion word table */
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ushort qadc_ccw[64];
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/* result word table, unsigned right justified */
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ushort qadc_rjurr[64];
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/* result word table, signed left justified */
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ushort qadc_ljsrr[64];
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/* result word table, unsigned left justified */
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ushort qadc_ljurr[64];
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} qadc5xx_t;
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/* QSMCM
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*/
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typedef struct qsmcm {
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ushort qsmcm_qsmcr;
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ushort qsmcm_qtest;
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ushort qsmcm_qdsci_il;
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ushort qsmcm_qspi_il;
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ushort qsmcm_scc1r0;
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ushort qsmcm_scc1r1;
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ushort qsmcm_sc1sr;
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ushort qsmcm_sc1dr;
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char res1[2];
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char res2[2];
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ushort qsmcm_portqs;
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u_char qsmcm_pqspar;
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u_char qsmcm_ddrqs;
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ushort qsmcm_spcr0;
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ushort qsmcm_spcr1;
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ushort qsmcm_spcr2;
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u_char qsmcm_spcr3;
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u_char qsmcm_spsr;
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ushort qsmcm_scc2r0;
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ushort qsmcm_scc2r1;
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ushort qsmcm_sc2sr;
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ushort qsmcm_sc2dr;
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ushort qsmcm_qsci1cr;
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ushort qsmcm_qsci1sr;
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ushort qsmcm_sctq[16];
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ushort qsmcm_scrq[16];
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char res3[212];
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ushort qsmcm_recram[32];
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ushort qsmcm_tranram[32];
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u_char qsmcm_comdram[32];
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char res[3616];
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} qsmcm5xx_t;
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/* MIOS
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*/
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typedef struct mios {
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ushort mios_mpwmsm0perr; /* mpwmsm0 */
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ushort mios_mpwmsm0pulr;
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ushort mios_mpwmsm0cntr;
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ushort mios_mpwmsm0scr;
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ushort mios_mpwmsm1perr; /* mpwmsm1 */
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ushort mios_mpwmsm1pulr;
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ushort mios_mpwmsm1cntr;
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ushort mios_mpwmsm1scr;
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ushort mios_mpwmsm2perr; /* mpwmsm2 */
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ushort mios_mpwmsm2pulr;
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ushort mios_mpwmsm2cntr;
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ushort mios_mpwmsm2scr;
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ushort mios_mpwmsm3perr; /* mpwmsm3 */
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ushort mios_mpwmsm3pulr;
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ushort mios_mpwmsm3cntr;
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ushort mios_mpwmsm3scr;
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char res1[16];
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ushort mios_mmcsm6cnt; /* mmcsm6 */
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ushort mios_mmcsm6mlr;
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ushort mios_mmcsm6scrd, mmcsm6scr;
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char res2[32];
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ushort mios_mdasm11ar; /* mdasm11 */
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ushort mios_mdasm11br;
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ushort mios_mdasm11scrd, mdasm11scr;
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ushort mios_mdasm12ar; /* mdasm12 */
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ushort mios_mdasm12br;
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ushort mios_mdasm12scrd, mdasm12scr;
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ushort mios_mdasm13ar; /* mdasm13 */
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ushort mios_mdasm13br;
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ushort mios_mdasm13scrd, mdasm13scr;
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ushort mios_mdasm14ar; /* mdasm14 */
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ushort mios_mdasm14br;
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ushort mios_mdasm14scrd, mdasm14scr;
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ushort mios_mdasm15ar; /* mdasm15 */
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ushort mios_mdasm15br;
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ushort mios_mdasm15scrd, mdasm15scr;
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ushort mios_mpwmsm16perr; /* mpwmsm16 */
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ushort mios_mpwmsm16pulr;
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ushort mios_mpwmsm16cntr;
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ushort mios_mpwmsm16scr;
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ushort mios_mpwmsm17perr; /* mpwmsm17 */
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ushort mios_mpwmsm17pulr;
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ushort mios_mpwmsm17cntr;
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ushort mios_mpwmsm17scr;
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ushort mios_mpwmsm18perr; /* mpwmsm18 */
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ushort mios_mpwmsm18pulr;
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ushort mios_mpwmsm18cntr;
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ushort mios_mpwmsm18scr;
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ushort mios_mpwmsm19perr; /* mpwmsm19 */
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ushort mios_mpwmsm19pulr;
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ushort mios_mpwmsm19cntr;
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ushort mios_mpwmsm19scr;
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char res3[16];
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ushort mios_mmcsm22cnt; /* mmcsm22 */
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ushort mios_mmcsm22mlr;
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ushort mios_mmcsm22scrd, mmcsm22scr;
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char res4[32];
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ushort mios_mdasm27ar; /* mdasm27 */
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ushort mios_mdasm27br;
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ushort mios_mdasm27scrd, mdasm27scr;
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ushort mios_mdasm28ar; /*mdasm28 */
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ushort mios_mdasm28br;
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ushort mios_mdasm28scrd, mdasm28scr;
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ushort mios_mdasm29ar; /* mdasm29 */
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ushort mios_mdasm29br;
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ushort mios_mdasm29scrd, mdasm29scr;
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ushort mios_mdasm30ar; /* mdasm30 */
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ushort mios_mdasm30br;
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ushort mios_mdasm30scrd, mdasm30scr;
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ushort mios_mdasm31ar; /* mdasm31 */
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ushort mios_mdasm31br;
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ushort mios_mdasm31scrd, mdasm31scr;
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ushort mios_mpiosm32dr;
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ushort mios_mpiosm32ddr;
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char res5[1788];
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ushort mios_mios1tpcr;
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char mios_res13[2];
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ushort mios_mios1vnr;
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ushort mios_mios1mcr;
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char res6[12];
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ushort mios_res42z;
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ushort mios_mcpsmscr;
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char res7[1000];
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ushort mios_mios1sr0;
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char res12[2];
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ushort mios_mios1er0;
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ushort mios_mios1rpr0;
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char res8[40];
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ushort mios_mios1lvl0;
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char res9[14];
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ushort mios_mios1sr1;
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char res10[2];
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ushort mios_mios1er1;
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ushort mios_mios1rpr1;
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char res11[40];
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ushort mios_mios1lvl1;
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char res13[1038];
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} mios5xx_t;
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/* Toucan Module
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*/
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typedef struct tcan {
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ushort tcan_tcnmcr;
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ushort tcan_cantcr;
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ushort tcan_canicr;
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u_char tcan_canctrl0;
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u_char tcan_canctrl1;
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u_char tcan_presdiv;
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u_char tcan_canctrl2;
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ushort tcan_timer;
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char res1[4];
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ushort tcan_rxgmskhi;
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ushort tcan_rxgmsklo;
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ushort tcan_rx14mskhi;
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ushort tcan_rx14msklo;
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ushort tcan_rx15mskhi;
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ushort tcan_rx15msklo;
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char res2[4];
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ushort tcan_estat;
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ushort tcan_imask;
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ushort tcan_iflag;
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u_char tcan_rxectr;
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u_char tcan_txectr;
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char res3[88];
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struct {
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ushort scr;
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ushort id_high;
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ushort id_low;
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u_char data[8];
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char res4[2];
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} tcan_mbuff[16];
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char res5[640];
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} tcan5xx_t;
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/* UIMB
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*/
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typedef struct uimb {
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uint uimb_umcr;
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char res1[12];
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uint uimb_utstcreg;
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char res2[12];
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uint uimb_uipend;
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} uimb5xx_t;
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/* Internal Memory Map MPC555
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*/
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typedef struct immap {
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char res1[262144]; /* CMF Flash A 256 Kbytes */
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char res2[196608]; /* CMF Flash B 192 Kbytes */
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char res3[2670592]; /* Reserved for Flash */
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sysconf5xx_t im_siu_conf; /* SIU Configuration */
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memctl5xx_t im_memctl; /* Memory Controller */
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sit5xx_t im_sit; /* System Integration Timers */
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car5xx_t im_clkrst; /* Clocks and Reset */
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sitk5xx_t im_sitk; /* System Integration Timer Keys*/
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cark8xx_t im_clkrstk; /* Clocks and Resert Keys */
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fl5xx_t im_fla; /* Flash Module A */
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fl5xx_t im_flb; /* Flash Module B */
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char res4[14208]; /* Reserved for SIU */
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dprc5xx_t im_dprc; /* Dpram Control Register */
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char res5[8180]; /* Reserved */
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char dptram[6144]; /* Dptram */
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char res6[2048]; /* Reserved */
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tpu5xx_t im_tpua; /* Time Proessing Unit A */
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tpu5xx_t im_tpub; /* Time Processing Unit B */
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qadc5xx_t im_qadca; /* QADC A */
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qadc5xx_t im_qadcb; /* QADC B */
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qsmcm5xx_t im_qsmcm; /* SCI and SPI */
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mios5xx_t im_mios; /* MIOS */
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tcan5xx_t im_tcana; /* Toucan A */
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tcan5xx_t im_tcanb; /* Toucan B */
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char res7[1792]; /* Reserved */
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uimb5xx_t im_uimb; /* UIMB */
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} immap_t;
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#endif /* __IMMAP_5XX__ */
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