upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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45 lines
1.3 KiB
45 lines
1.3 KiB
/*
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* Copyright (c) 2010, Applied Micro Circuits Corporation
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* Author: Tirumala R Marri <tmarri@apm.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <ppc_asm.tmpl>
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#include <config.h>
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#include <asm/mmu.h>
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#include <asm/ppc4xx.h>
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/**************************************************************************
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* TLB TABLE
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*
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* This table is used by the cpu boot code to setup the initial tlb
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* entries. Rather than make broad assumptions in the cpu source tree,
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* this table lets each board set things up however they like.
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*
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* Pointer to the table is returned in r1
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*
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*************************************************************************/
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.section .bootpg,"ax"
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.globl tlbtab
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tlbtab:
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tlbtab_start
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/* TLB 0 */
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tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR,
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4, AC_RWX | SA_G)
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/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
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tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR,
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0, AC_RWX | SA_G)
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/* TLB-entry for OCM */
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tlbentry(CONFIG_SYS_OCM_BASE, SZ_64K, 0x00040000, 4,
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AC_RWX | SA_I)
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/* TLB-entry for Local Configuration registers => peripherals */
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tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K,
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CONFIG_SYS_PERIPHERAL_BASE, 4, AC_RWX | SA_IG)
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tlbtab_end
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