upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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225 lines
5.3 KiB
225 lines
5.3 KiB
#ifndef __LPC2292_REGISTERS_H
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#define __LPC2292_REGISTERS_H
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#include <config.h>
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/* Macros for reading/writing registers */
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#define PUT8(reg, value) (*(volatile unsigned char*)(reg) = (value))
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#define PUT16(reg, value) (*(volatile unsigned short*)(reg) = (value))
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#define PUT32(reg, value) (*(volatile unsigned int*)(reg) = (value))
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#define GET8(reg) (*(volatile unsigned char*)(reg))
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#define GET16(reg) (*(volatile unsigned short*)(reg))
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#define GET32(reg) (*(volatile unsigned int*)(reg))
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/* External Memory Controller */
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#define BCFG0 0xFFE00000 /* 32-bits */
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#define BCFG1 0xFFE00004 /* 32-bits */
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#define BCFG2 0xFFE00008 /* 32-bits */
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#define BCFG3 0xFFE0000c /* 32-bits */
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/* System Control Block */
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#define EXTINT 0xE01FC140
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#define EXTWAKE 0xE01FC144
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#define EXTMODE 0xE01FC148
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#define EXTPOLAR 0xE01FC14C
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#define MEMMAP 0xE01FC040
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#define PLLCON 0xE01FC080
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#define PLLCFG 0xE01FC084
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#define PLLSTAT 0xE01FC088
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#define PLLFEED 0xE01FC08C
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#define PCON 0xE01FC0C0
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#define PCONP 0xE01FC0C4
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#define VPBDIV 0xE01FC100
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/* Memory Acceleration Module */
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#define MAMCR 0xE01FC000
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#define MAMTIM 0xE01FC004
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/* Vectored Interrupt Controller */
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#define VICIRQStatus 0xFFFFF000
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#define VICFIQStatus 0xFFFFF004
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#define VICRawIntr 0xFFFFF008
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#define VICIntSelect 0xFFFFF00C
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#define VICIntEnable 0xFFFFF010
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#define VICIntEnClr 0xFFFFF014
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#define VICSoftInt 0xFFFFF018
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#define VICSoftIntClear 0xFFFFF01C
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#define VICProtection 0xFFFFF020
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#define VICVectAddr 0xFFFFF030
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#define VICDefVectAddr 0xFFFFF034
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#define VICVectAddr0 0xFFFFF100
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#define VICVectAddr1 0xFFFFF104
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#define VICVectAddr2 0xFFFFF108
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#define VICVectAddr3 0xFFFFF10C
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#define VICVectAddr4 0xFFFFF110
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#define VICVectAddr5 0xFFFFF114
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#define VICVectAddr6 0xFFFFF118
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#define VICVectAddr7 0xFFFFF11C
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#define VICVectAddr8 0xFFFFF120
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#define VICVectAddr9 0xFFFFF124
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#define VICVectAddr10 0xFFFFF128
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#define VICVectAddr11 0xFFFFF12C
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#define VICVectAddr12 0xFFFFF130
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#define VICVectAddr13 0xFFFFF134
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#define VICVectAddr14 0xFFFFF138
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#define VICVectAddr15 0xFFFFF13C
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#define VICVectCntl0 0xFFFFF200
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#define VICVectCntl1 0xFFFFF204
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#define VICVectCntl2 0xFFFFF208
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#define VICVectCntl3 0xFFFFF20C
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#define VICVectCntl4 0xFFFFF210
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#define VICVectCntl5 0xFFFFF214
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#define VICVectCntl6 0xFFFFF218
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#define VICVectCntl7 0xFFFFF21C
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#define VICVectCntl8 0xFFFFF220
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#define VICVectCntl9 0xFFFFF224
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#define VICVectCntl10 0xFFFFF228
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#define VICVectCntl11 0xFFFFF22C
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#define VICVectCntl12 0xFFFFF230
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#define VICVectCntl13 0xFFFFF234
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#define VICVectCntl14 0xFFFFF238
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#define VICVectCntl15 0xFFFFF23C
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/* Pin connect block */
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#define PINSEL0 0xE002C000 /* 32 bits */
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#define PINSEL1 0xE002C004 /* 32 bits */
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#define PINSEL2 0xE002C014 /* 32 bits */
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/* GPIO */
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#define IO0PIN 0xE0028000
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#define IO0SET 0xE0028004
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#define IO0DIR 0xE0028008
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#define IO0CLR 0xE002800C
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#define IO1PIN 0xE0028010
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#define IO1SET 0xE0028014
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#define IO1DIR 0xE0028018
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#define IO1CLR 0xE002801C
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#define IO2PIN 0xE0028020
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#define IO2SET 0xE0028024
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#define IO2DIR 0xE0028028
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#define IO2CLR 0xE002802C
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#define IO3PIN 0xE0028030
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#define IO3SET 0xE0028034
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#define IO3DIR 0xE0028038
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#define IO3CLR 0xE002803C
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/* Uarts */
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#define U0RBR 0xE000C000
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#define U0THR 0xE000C000
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#define U0IER 0xE000C004
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#define U0IIR 0xE000C008
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#define U0FCR 0xE000C008
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#define U0LCR 0xE000C00C
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#define U0LSR 0xE000C014
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#define U0SCR 0xE000C01C
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#define U0DLL 0xE000C000
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#define U0DLM 0xE000C004
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#define U1RBR 0xE0010000
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#define U1THR 0xE0010000
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#define U1IER 0xE0010004
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#define U1IIR 0xE0010008
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#define U1FCR 0xE0010008
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#define U1LCR 0xE001000C
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#define U1MCR 0xE0010010
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#define U1LSR 0xE0010014
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#define U1MSR 0xE0010018
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#define U1SCR 0xE001001C
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#define U1DLL 0xE0010000
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#define U1DLM 0xE0010004
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/* I2C */
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#define I2CONSET 0xE001C000
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#define I2STAT 0xE001C004
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#define I2DAT 0xE001C008
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#define I2ADR 0xE001C00C
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#define I2SCLH 0xE001C010
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#define I2SCLL 0xE001C014
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#define I2CONCLR 0xE001C018
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/* SPI */
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#define S0SPCR 0xE0020000
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#define S0SPSR 0xE0020004
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#define S0SPDR 0xE0020008
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#define S0SPCCR 0xE002000C
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#define S0SPINT 0xE002001C
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#define S1SPCR 0xE0030000
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#define S1SPSR 0xE0030004
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#define S1SPDR 0xE0030008
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#define S1SPCCR 0xE003000C
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#define S1SPINT 0xE003001C
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/* CAN controller */
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/* skip for now */
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/* Timers */
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#define T0IR 0xE0004000
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#define T0TCR 0xE0004004
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#define T0TC 0xE0004008
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#define T0PR 0xE000400C
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#define T0PC 0xE0004010
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#define T0MCR 0xE0004014
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#define T0MR0 0xE0004018
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#define T0MR1 0xE000401C
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#define T0MR2 0xE0004020
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#define T0MR3 0xE0004024
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#define T0CCR 0xE0004028
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#define T0CR0 0xE000402C
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#define T0CR1 0xE0004030
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#define T0CR2 0xE0004034
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#define T0CR3 0xE0004038
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#define T0EMR 0xE000403C
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#define T1IR 0xE0008000
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#define T1TCR 0xE0008004
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#define T1TC 0xE0008008
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#define T1PR 0xE000800C
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#define T1PC 0xE0008010
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#define T1MCR 0xE0008014
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#define T1MR0 0xE0008018
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#define T1MR1 0xE000801C
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#define T1MR2 0xE0008020
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#define T1MR3 0xE0008024
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#define T1CCR 0xE0008028
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#define T1CR0 0xE000802C
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#define T1CR1 0xE0008030
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#define T1CR2 0xE0008034
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#define T1CR3 0xE0008038
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#define T1EMR 0xE000803C
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/* PWM */
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/* skip for now */
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/* A/D converter */
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/* skip for now */
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/* Real Time Clock */
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/* skip for now */
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/* Watchdog */
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#define WDMOD 0xE0000000
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#define WDTC 0xE0000004
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#define WDFEED 0xE0000008
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#define WDTV 0xE000000C
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/* EmbeddedICE LOGIC */
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/* skip for now */
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#endif
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