upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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334 lines
8.7 KiB
334 lines
8.7 KiB
/*
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* (C) Copyright 2010
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* Texas Instruments Incorporated, <www.ti.com>
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* Steve Sakoman <steve@sakoman.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/gpio.h>
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#include "panda_mux_data.h"
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#ifdef CONFIG_USB_EHCI
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#include <usb.h>
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#include <asm/arch/ehci.h>
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#include <asm/ehci-omap.h>
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#endif
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#define PANDA_ULPI_PHY_TYPE_GPIO 182
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#define PANDA_BOARD_ID_1_GPIO 101
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#define PANDA_ES_BOARD_ID_1_GPIO 48
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#define PANDA_BOARD_ID_2_GPIO 171
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#define PANDA_ES_BOARD_ID_3_GPIO 3
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#define PANDA_ES_BOARD_ID_4_GPIO 2
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DECLARE_GLOBAL_DATA_PTR;
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const struct omap_sysinfo sysinfo = {
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"Board: OMAP4 Panda\n"
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};
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struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
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/**
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* @brief board_init
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*
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* @return 0
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*/
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int board_init(void)
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{
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gpmc_init();
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gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
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gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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return 0;
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}
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/*
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* Routine: get_board_revision
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* Description: Detect if we are running on a panda revision A1-A6,
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* or an ES panda board. This can be done by reading
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* the level of GPIOs and checking the processor revisions.
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* This should result in:
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* Panda 4430:
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* GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5
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* GPIO171, GPIO101, GPIO182: 1 0 1 => A6
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* Panda ES:
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* GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2
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* GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3
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*/
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int get_board_revision(void)
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{
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int board_id0, board_id1, board_id2;
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int board_id3, board_id4;
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int board_id;
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int processor_rev = omap_revision();
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/* Setup the mux for the common board ID pins (gpio 171 and 182) */
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writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0);
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writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT);
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board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
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board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
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if ((processor_rev >= OMAP4460_ES1_0 &&
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processor_rev <= OMAP4460_ES1_1)) {
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/*
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* Setup the mux for the ES specific board ID pins (gpio 101,
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* 2 and 3.
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*/
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writew((IEN | M3), (*ctrl)->control_padconf_core_base +
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GPMC_A24);
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writew((IEN | M3), (*ctrl)->control_padconf_core_base +
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UNIPRO_RY0);
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writew((IEN | M3), (*ctrl)->control_padconf_core_base +
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UNIPRO_RX1);
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board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO);
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board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO);
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board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO);
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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setenv("board_name", "panda-es");
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#endif
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board_id = ((board_id4 << 4) | (board_id3 << 3) |
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(board_id2 << 2) | (board_id1 << 1) | (board_id0));
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} else {
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/* Setup the mux for the Ax specific board ID pins (gpio 101) */
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writew((IEN | M3), (*ctrl)->control_padconf_core_base +
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FREF_CLK2_OUT);
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board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO);
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board_id = ((board_id2 << 2) | (board_id1 << 1) | (board_id0));
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3))
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setenv("board_name", "panda-a4");
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#endif
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}
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return board_id;
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}
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/**
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* is_panda_es_rev_b3() - Detect if we are running on rev B3 of panda board ES
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*
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*
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* Detect if we are running on B3 version of ES panda board,
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* This can be done by reading the level of GPIO 171 and checking the
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* processor revisions.
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* GPIO171: 1 => Panda ES Rev B3
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*
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* Return : return 1 if Panda ES Rev B3 , else return 0
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*/
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u8 is_panda_es_rev_b3(void)
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{
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int processor_rev = omap_revision();
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int ret = 0;
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if ((processor_rev >= OMAP4460_ES1_0 &&
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processor_rev <= OMAP4460_ES1_1)) {
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/* Setup the mux for the common board ID pins (gpio 171) */
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writew((IEN | M3),
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(*ctrl)->control_padconf_core_base + UNIPRO_TX0);
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/* if processor_rev is panda ES and GPIO171 is 1,it is rev b3 */
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ret = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
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}
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return ret;
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}
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#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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/*
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* emif_get_reg_dump() - emif_get_reg_dump strong function
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*
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* @emif_nr - emif base
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* @regs - reg dump of timing values
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*
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* Strong function to override emif_get_reg_dump weak function in sdram_elpida.c
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*/
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void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
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{
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u32 omap4_rev = omap_revision();
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/* Same devices and geometry on both EMIFs */
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if (omap4_rev == OMAP4430_ES1_0)
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*regs = &emif_regs_elpida_380_mhz_1cs;
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else if (omap4_rev == OMAP4430_ES2_0)
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*regs = &emif_regs_elpida_200_mhz_2cs;
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else if (omap4_rev == OMAP4430_ES2_3)
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*regs = &emif_regs_elpida_400_mhz_1cs;
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else if (omap4_rev < OMAP4470_ES1_0) {
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if(is_panda_es_rev_b3())
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*regs = &emif_regs_elpida_400_mhz_1cs;
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else
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*regs = &emif_regs_elpida_400_mhz_2cs;
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}
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else
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*regs = &emif_regs_elpida_400_mhz_1cs;
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}
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void emif_get_dmm_regs(const struct dmm_lisa_map_regs
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**dmm_lisa_regs)
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{
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u32 omap_rev = omap_revision();
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if (omap_rev == OMAP4430_ES1_0)
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*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
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else if (omap_rev == OMAP4430_ES2_3)
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*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
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else if (omap_rev < OMAP4460_ES1_0)
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*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
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else
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*dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
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}
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#endif
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/**
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* @brief misc_init_r - Configure Panda board specific configurations
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* such as power configurations, ethernet initialization as phase2 of
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* boot sequence
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*
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* @return 0
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*/
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int misc_init_r(void)
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{
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int phy_type;
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u32 auxclk, altclksrc;
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/* EHCI is not supported on ES1.0 */
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if (omap_revision() == OMAP4430_ES1_0)
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return 0;
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get_board_revision();
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gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
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phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
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if (phy_type == 1) {
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/* ULPI PHY supplied by auxclk3 derived from sys_clk */
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debug("ULPI PHY supplied by auxclk3\n");
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auxclk = readl(&scrm->auxclk3);
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/* Select sys_clk */
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auxclk &= ~AUXCLK_SRCSELECT_MASK;
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auxclk |= AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
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/* Set the divisor to 2 */
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auxclk &= ~AUXCLK_CLKDIV_MASK;
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auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
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/* Request auxilary clock #3 */
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auxclk |= AUXCLK_ENABLE_MASK;
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writel(auxclk, &scrm->auxclk3);
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} else {
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/* ULPI PHY supplied by auxclk1 derived from PER dpll */
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debug("ULPI PHY supplied by auxclk1\n");
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auxclk = readl(&scrm->auxclk1);
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/* Select per DPLL */
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auxclk &= ~AUXCLK_SRCSELECT_MASK;
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auxclk |= AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT;
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/* Set the divisor to 16 */
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auxclk &= ~AUXCLK_CLKDIV_MASK;
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auxclk |= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT;
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/* Request auxilary clock #3 */
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auxclk |= AUXCLK_ENABLE_MASK;
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writel(auxclk, &scrm->auxclk1);
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}
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altclksrc = readl(&scrm->altclksrc);
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/* Activate alternate system clock supplier */
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altclksrc &= ~ALTCLKSRC_MODE_MASK;
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altclksrc |= ALTCLKSRC_MODE_ACTIVE;
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/* enable clocks */
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altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
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writel(altclksrc, &scrm->altclksrc);
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omap_die_id_usbethaddr();
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return 0;
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}
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void set_muxconf_regs_essential(void)
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{
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do_set_mux((*ctrl)->control_padconf_core_base,
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core_padconf_array_essential,
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sizeof(core_padconf_array_essential) /
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sizeof(struct pad_conf_entry));
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do_set_mux((*ctrl)->control_padconf_wkup_base,
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wkup_padconf_array_essential,
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sizeof(wkup_padconf_array_essential) /
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sizeof(struct pad_conf_entry));
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if (omap_revision() >= OMAP4460_ES1_0)
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do_set_mux((*ctrl)->control_padconf_wkup_base,
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wkup_padconf_array_essential_4460,
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sizeof(wkup_padconf_array_essential_4460) /
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sizeof(struct pad_conf_entry));
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}
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#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
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int board_mmc_init(bd_t *bis)
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{
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return omap_mmc_init(0, 0, 0, -1, -1);
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}
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#endif
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#ifdef CONFIG_USB_EHCI
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static struct omap_usbhs_board_data usbhs_bdata = {
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.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
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.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
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.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
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};
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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int ret;
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unsigned int utmi_clk;
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/* Now we can enable our port clocks */
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utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
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utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
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setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
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ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
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if (ret < 0)
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return ret;
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return 0;
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}
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int ehci_hcd_stop(int index)
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{
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return omap_ehci_hcd_stop();
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}
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#endif
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/*
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* get_board_rev() - get board revision
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*/
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u32 get_board_rev(void)
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{
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return 0x20;
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}
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