upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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268 lines
6.0 KiB
268 lines
6.0 KiB
/*
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* Copyright (C) 2005-2008 Atmel Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/ptrace.h>
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#include <asm/sysreg.h>
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#define SYSREG_MMUCR_I_OFFSET 2
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#define SYSREG_MMUCR_S_OFFSET 4
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#define SR_INIT (SYSREG_BIT(GM) | SYSREG_BIT(EM) | SYSREG_BIT(M0))
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/* due to errata (unreliable branch folding) clear FE bit explicitly */
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#define CPUCR_INIT ((SYSREG_BIT(BI) | SYSREG_BIT(BE) \
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| SYSREG_BIT(RE) | SYSREG_BIT(IBE) \
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| SYSREG_BIT(IEE)) & ~SYSREG_BIT(FE))
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/*
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* To save some space, we use the same entry point for
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* exceptions and reset. This avoids lots of alignment padding
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* since the reset vector is always suitably aligned.
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*/
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.section .exception.text, "ax", @progbits
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.global _start
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.global _evba
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.type _start, @function
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.type _evba, @function
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_start:
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.size _start, 0
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_evba:
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.org 0x00
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rjmp unknown_exception /* Unrecoverable exception */
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.org 0x04
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rjmp unknown_exception /* TLB multiple hit */
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.org 0x08
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rjmp unknown_exception /* Bus error data fetch */
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.org 0x0c
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rjmp unknown_exception /* Bus error instruction fetch */
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.org 0x10
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rjmp unknown_exception /* NMI */
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.org 0x14
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rjmp unknown_exception /* Instruction address */
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.org 0x18
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rjmp unknown_exception /* ITLB protection */
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.org 0x1c
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rjmp unknown_exception /* Breakpoint */
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.org 0x20
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rjmp unknown_exception /* Illegal opcode */
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.org 0x24
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rjmp unknown_exception /* Unimplemented instruction */
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.org 0x28
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rjmp unknown_exception /* Privilege violation */
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.org 0x2c
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rjmp unknown_exception /* Floating-point */
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.org 0x30
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rjmp unknown_exception /* Coprocessor absent */
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.org 0x34
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rjmp unknown_exception /* Data Address (read) */
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.org 0x38
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rjmp unknown_exception /* Data Address (write) */
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.org 0x3c
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rjmp unknown_exception /* DTLB Protection (read) */
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.org 0x40
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rjmp unknown_exception /* DTLB Protection (write) */
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.org 0x44
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rjmp unknown_exception /* DTLB Modified */
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.org 0x50 /* ITLB Miss */
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pushm r8-r12,lr
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rjmp 1f
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.org 0x60 /* DTLB Miss (read) */
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pushm r8-r12,lr
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rjmp 1f
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.org 0x70 /* DTLB Miss (write) */
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pushm r8-r12,lr
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1: mov r12, sp
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rcall mmu_handle_tlb_miss
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popm r8-r12,lr
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brne unknown_exception
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rete
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.size _evba, . - _evba
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.align 2
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.type unknown_exception, @function
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unknown_exception:
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/* Figure out whether we're handling an exception (Exception
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* mode) or just booting (Supervisor mode). */
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csrfcz SYSREG_M1_OFFSET
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brcc at32ap_cpu_bootstrap
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/* This is an exception. Complain. */
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pushm r0-r12
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sub r8, sp, REG_R12 - REG_R0 - 4
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mov r9, lr
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mfsr r10, SYSREG_RAR_EX
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mfsr r11, SYSREG_RSR_EX
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pushm r8-r11
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mfsr r12, SYSREG_ECR
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mov r11, sp
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rcall do_unknown_exception
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1: rjmp 1b
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/* The COUNT/COMPARE timer interrupt handler */
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.global timer_interrupt_handler
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.type timer_interrupt_handler,@function
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.align 2
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timer_interrupt_handler:
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/*
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* Increment timer_overflow and re-write COMPARE with 0xffffffff.
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*
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* We're running at interrupt level 3, so we don't need to save
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* r8-r12 or lr to the stack.
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*/
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lda.w r8, timer_overflow
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ld.w r9, r8[0]
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mov r10, -1
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mtsr SYSREG_COMPARE, r10
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sub r9, -1
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st.w r8[0], r9
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rete
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/*
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* CPU bootstrap after reset is handled here. SoC code may
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* override this in case they need to initialize oscillators,
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* etc.
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*/
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.section .text.at32ap_cpu_bootstrap, "ax", @progbits
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.global at32ap_cpu_bootstrap
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.weak at32ap_cpu_bootstrap
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.type at32ap_cpu_bootstrap, @function
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.align 2
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at32ap_cpu_bootstrap:
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/* Reset the Status Register */
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mov r0, lo(SR_INIT)
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orh r0, hi(SR_INIT)
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mtsr SYSREG_SR, r0
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/* Reset CPUCR and invalidate the BTB */
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mov r2, CPUCR_INIT
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mtsr SYSREG_CPUCR, r2
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/* Flush the caches */
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mov r1, 0
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cache r1[4], 8
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cache r1[0], 0
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sync 0
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/* Reset the MMU to default settings */
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mov r0, SYSREG_BIT(MMUCR_S) | SYSREG_BIT(MMUCR_I)
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mtsr SYSREG_MMUCR, r0
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/* Internal RAM should not need any initialization. We might
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have to initialize external RAM here if the part doesn't
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have internal RAM (or we may use the data cache) */
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/* Jump to cacheable segment */
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lddpc pc, 1f
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.align 2
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1: .long at32ap_low_level_init
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.size _start, . - _start
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/* Common CPU bootstrap code after oscillator/cache/etc. init */
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.section .text.avr32ap_low_level_init, "ax", @progbits
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.global at32ap_low_level_init
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.type at32ap_low_level_init, @function
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.align 2
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at32ap_low_level_init:
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lddpc sp, sp_init
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/* Initialize the GOT pointer */
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lddpc r6, got_init
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3: rsub r6, pc
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/* Let's go */
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rjmp board_init_f
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.align 2
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.type sp_init,@object
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sp_init:
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.long CONFIG_SYS_INIT_SP_ADDR
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got_init:
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.long 3b - _GLOBAL_OFFSET_TABLE_
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/*
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* void relocate_code(new_sp, new_gd, monitor_addr)
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*
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* Relocate the u-boot image into RAM and continue from there.
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* Does not return.
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*/
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.section .text.relocate_code,"ax",@progbits
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.global relocate_code
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.type relocate_code,@function
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relocate_code:
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mov sp, r12 /* use new stack */
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mov r12, r11 /* save new_gd */
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mov r11, r10 /* save destination address */
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/* copy .text section and flush the cache along the way */
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lda.w r8, _text
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lda.w r9, _etext
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sub lr, r10, r8 /* relocation offset */
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1: ldm r8++, r0-r3
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stm r10, r0-r3
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sub r10, -16
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ldm r8++, r0-r3
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stm r10, r0-r3
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sub r10, -16
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cp.w r8, r9
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cache r10[-4], 0x0d /* dcache clean/invalidate */
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cache r10[-4], 0x01 /* icache invalidate */
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brlt 1b
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/* flush write buffer */
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sync 0
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/* copy data sections */
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lda.w r9, _edata
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1: ld.d r0, r8++
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st.d r10++, r0
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cp.w r8, r9
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brlt 1b
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/* zero out .bss */
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mov r0, 0
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mov r1, 0
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lda.w r9, __bss_end
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sub r9, r8
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1: st.d r10++, r0
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sub r9, 8
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brgt 1b
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/* jump to RAM */
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sub r0, pc, . - in_ram
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add pc, r0, lr
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.align 2
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in_ram:
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/* find the new GOT and relocate it */
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lddpc r6, got_init_reloc
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3: rsub r6, pc
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mov r8, r6
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lda.w r9, _egot
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lda.w r10, _got
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sub r9, r10
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1: ld.w r0, r8[0]
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add r0, lr
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st.w r8++, r0
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sub r9, 4
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brgt 1b
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/* Move the exception handlers */
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mfsr r2, SYSREG_EVBA
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add r2, lr
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mtsr SYSREG_EVBA, r2
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/* Do the rest of the initialization sequence */
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call board_init_r
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.align 2
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got_init_reloc:
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.long 3b - _GLOBAL_OFFSET_TABLE_
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.size relocate_code, . - relocate_code
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