upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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558 lines
14 KiB
558 lines
14 KiB
/*
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* (C) Copyright 2007-2013
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/ppc440.h>
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#include <asm/processor.h>
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#include <asm/ppc4xx-gpio.h>
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#include <asm/io.h>
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#include <post.h>
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#include <flash.h>
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#include <mtd/cfi_flash.h>
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DECLARE_GLOBAL_DATA_PTR;
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static phys_addr_t lwmon5_cfi_flash_bank_addr[2] = CONFIG_SYS_FLASH_BANKS_LIST;
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ulong flash_get_size(ulong base, int banknum);
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int misc_init_r_kbd(void);
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int board_early_init_f(void)
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{
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u32 sdr0_pfc1, sdr0_pfc2;
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u32 reg;
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/* PLB Write pipelining disabled. Denali Core workaround */
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mtdcr(PLB4A0_ACR, 0xDE000000);
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mtdcr(PLB4A1_ACR, 0xDE000000);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
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mtdcr(UIC0ER, 0x00000000); /* disable all */
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mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */
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mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */
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mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */
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mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC1ER, 0x00000000); /* disable all */
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mtdcr(UIC1CR, 0x00000000); /* all non-critical */
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mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */
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mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */
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mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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mtdcr(UIC2ER, 0x00000000); /* disable all */
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mtdcr(UIC2CR, 0x00000000); /* all non-critical */
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mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */
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mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */
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mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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/* Trace Pins are disabled. SDR0_PFC0 Register */
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mtsdr(SDR0_PFC0, 0x0);
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/* select Ethernet pins */
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mfsdr(SDR0_PFC1, sdr0_pfc1);
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/* SMII via ZMII */
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sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
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SDR0_PFC1_SELECT_CONFIG_6;
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mfsdr(SDR0_PFC2, sdr0_pfc2);
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sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
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SDR0_PFC2_SELECT_CONFIG_6;
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/* enable SPI (SCP) */
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sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
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mtsdr(SDR0_PFC2, sdr0_pfc2);
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mtsdr(SDR0_PFC1, sdr0_pfc1);
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mtsdr(SDR0_PFC4, 0x80000000);
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/* PCI arbiter disabled */
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/* PCI Host Configuration disbaled */
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mfsdr(SDR0_PCI0, reg);
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reg = 0;
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mtsdr(SDR0_PCI0, 0x00000000 | reg);
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gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
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#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
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/* enable the LSB transmitter */
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gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
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/* enable the CAN transmitter */
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gpio_write_bit(CONFIG_SYS_GPIO_CAN_ENABLE, 1);
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reg = 0; /* reuse as counter */
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out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
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in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
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& ~CONFIG_SYS_DSPIC_TEST_MASK);
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while (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
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udelay(1000);
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}
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if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
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/* set "boot error" flag */
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out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
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in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
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CONFIG_SYS_DSPIC_TEST_MASK);
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}
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#endif
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/*
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* Reset PHY's:
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* The PHY's need a 2nd reset pulse, since the MDIO address is latched
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* upon reset, and with the first reset upon powerup, the addresses are
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* not latched reliable, since the IRQ line is multiplexed with an
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* MDIO address. A 2nd reset at this time will make sure, that the
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* correct address is latched.
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*/
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gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
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gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
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udelay(1000);
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gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
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gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
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udelay(1000);
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gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
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gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
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return 0;
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}
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/*
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* Override weak default with board specific version
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*/
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phys_addr_t cfi_flash_bank_addr(int bank)
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{
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return lwmon5_cfi_flash_bank_addr[bank];
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}
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/*
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* Override the weak default mapping function with a board specific one
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*/
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u32 flash_get_bank_size(int cs, int idx)
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{
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return flash_info[idx].size;
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}
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int board_early_init_r(void)
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{
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u32 val0, val1;
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/*
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* lwmon5 is manufactured in 2 different board versions:
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* The lwmon5a board has 64MiB NOR flash instead of the
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* 128MiB of the original lwmon5. Unfortunately the CFI driver
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* will report 2 banks of 64MiB even for the smaller flash
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* chip, since the bank is mirrored. To fix this, we bring
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* one bank into CFI query mode and read its response. This
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* enables us to detect the real number of flash devices/
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* banks which will be used later on by the common CFI driver.
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*/
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/* Put bank 0 into CFI command mode and read */
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out_be32((void *)CONFIG_SYS_FLASH0, 0x00980098);
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val0 = in_be32((void *)CONFIG_SYS_FLASH0 + FLASH_OFFSET_CFI_RESP);
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val1 = in_be32((void *)CONFIG_SYS_FLASH1 + FLASH_OFFSET_CFI_RESP);
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/* Reset flash again out of query mode */
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out_be32((void *)CONFIG_SYS_FLASH0, 0x00f000f0);
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/* When not identical, we have 2 different flash devices/banks */
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if (val0 != val1)
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return 0;
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/*
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* Now we're sure that we're running on a LWMON5a board with
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* only 64MiB NOR flash in one bank:
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*
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* Set flash base address and bank count for CFI driver probing.
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*/
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cfi_flash_num_flash_banks = 1;
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lwmon5_cfi_flash_bank_addr[0] = CONFIG_SYS_FLASH0;
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return 0;
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}
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int misc_init_r(void)
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{
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u32 pbcr;
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int size_val = 0;
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u32 reg;
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#ifndef CONFIG_LCD4_LWMON5
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unsigned long usb2d0cr = 0;
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unsigned long usb2phy0cr, usb2h0cr = 0;
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unsigned long sdr0_pfc1, sdr0_srst;
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#endif
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/*
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* FLASH stuff...
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*/
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/* Re-do sizing to get full correct info */
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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mfebc(PB0CR, pbcr);
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size_val = ffs(gd->bd->bi_flashsize) - 21;
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pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
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mtebc(PB0CR, pbcr);
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/*
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* Re-check to get correct base address
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*/
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flash_get_size(gd->bd->bi_flashstart, 0);
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/* Monitor protection ON by default */
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flash_protect(FLAG_PROTECT_SET, -CONFIG_SYS_MONITOR_LEN, 0xffffffff,
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&flash_info[cfi_flash_num_flash_banks - 1]);
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/* Env protection ON by default */
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flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR_REDUND,
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CONFIG_ENV_ADDR_REDUND + 2 * CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[cfi_flash_num_flash_banks - 1]);
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#ifndef CONFIG_LCD4_LWMON5
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/*
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* USB suff...
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*/
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/* Reset USB */
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/* Reset of USB2PHY0 must be active at least 10 us */
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mtsdr(SDR0_SRST0, SDR0_SRST0_USB2H | SDR0_SRST0_USB2D);
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udelay(2000);
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mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY | SDR0_SRST1_USB2HUTMI |
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SDR0_SRST1_USB2HPHY | SDR0_SRST1_OPBA2 |
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SDR0_SRST1_PLB42OPB1 | SDR0_SRST1_OPB2PLB40);
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udelay(2000);
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/* Errata CHIP_6 */
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/* 1. Set internal PHY configuration */
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/* SDR Setting */
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mfsdr(SDR0_PFC1, sdr0_pfc1);
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mfsdr(SDR0_USB0, usb2d0cr);
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mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mfsdr(SDR0_USB2H0CR, usb2h0cr);
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usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_XOCLK_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
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usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_WDINT_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
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usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DVBUS_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN; /*1*/
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usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_DWNSTR_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
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usb2phy0cr = usb2phy0cr & ~SDR0_USB2PHY0CR_UTMICN_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
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/*
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* An 8-bit/60MHz interface is the only possible alternative
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* when connecting the Device to the PHY
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*/
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usb2h0cr = usb2h0cr & ~SDR0_USB2H0CR_WDINT_MASK;
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usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
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mtsdr(SDR0_PFC1, sdr0_pfc1);
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mtsdr(SDR0_USB0, usb2d0cr);
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mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mtsdr(SDR0_USB2H0CR, usb2h0cr);
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/* 2. De-assert internal PHY reset */
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mfsdr(SDR0_SRST1, sdr0_srst);
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sdr0_srst = sdr0_srst & ~SDR0_SRST1_USB20PHY;
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mtsdr(SDR0_SRST1, sdr0_srst);
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/* 3. Wait for more than 1 ms */
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udelay(2000);
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/* 4. De-assert USB 2.0 Host main reset */
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mfsdr(SDR0_SRST0, sdr0_srst);
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sdr0_srst = sdr0_srst &~ SDR0_SRST0_USB2H;
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mtsdr(SDR0_SRST0, sdr0_srst);
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udelay(1000);
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/* 5. De-assert reset of OPB2 cores */
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mfsdr(SDR0_SRST1, sdr0_srst);
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sdr0_srst = sdr0_srst &~ SDR0_SRST1_PLB42OPB1;
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sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPB2PLB40;
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sdr0_srst = sdr0_srst &~ SDR0_SRST1_OPBA2;
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mtsdr(SDR0_SRST1, sdr0_srst);
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udelay(1000);
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/* 6. Set EHCI Configure FLAG */
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/* 7. Reassert internal PHY reset: */
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mtsdr(SDR0_SRST1, SDR0_SRST1_USB20PHY);
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udelay(1000);
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#endif
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/*
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* Clear resets
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*/
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mtsdr(SDR0_SRST1, 0x00000000);
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mtsdr(SDR0_SRST0, 0x00000000);
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#ifndef CONFIG_LCD4_LWMON5
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printf("USB: Host(int phy) Device(ext phy)\n");
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#endif
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/*
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* Clear PLB4A0_ACR[WRP]
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* This fix will make the MAL burst disabling patch for the Linux
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* EMAC driver obsolete.
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*/
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reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
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mtdcr(PLB4A0_ACR, reg);
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#ifndef CONFIG_LCD4_LWMON5
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/*
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* Init matrix keyboard
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*/
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misc_init_r_kbd();
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#endif
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return 0;
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}
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int checkboard(void)
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{
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char buf[64];
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int i = getenv_f("serial#", buf, sizeof(buf));
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printf("Board: %s", __stringify(CONFIG_HOSTNAME));
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if (i > 0) {
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puts(", serial# ");
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puts(buf);
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}
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putc('\n');
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return (0);
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}
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void hw_watchdog_reset(void)
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{
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int val;
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#if defined(CONFIG_WD_MAX_RATE)
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unsigned long long ct = get_ticks();
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/*
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* Don't allow watch-dog triggering more frequently than
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* the predefined value CONFIG_WD_MAX_RATE [ticks].
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*/
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if (ct >= gd->arch.wdt_last) {
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if ((ct - gd->arch.wdt_last) < CONFIG_WD_MAX_RATE)
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return;
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} else {
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/* Time base counter had been reset */
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if (((unsigned long long)(-1) - gd->arch.wdt_last + ct) <
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CONFIG_WD_MAX_RATE)
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return;
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}
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gd->arch.wdt_last = get_ticks();
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#endif
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/*
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* Toggle watchdog output
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*/
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val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
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gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
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}
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int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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if (argc < 2)
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return cmd_usage(cmdtp);
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if ((strcmp(argv[1], "on") == 0))
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gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
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else if ((strcmp(argv[1], "off") == 0))
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gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
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else
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return cmd_usage(cmdtp);
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return 0;
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}
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U_BOOT_CMD(
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eepromwp, 2, 0, do_eeprom_wp,
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"eeprom write protect off/on",
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"<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
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);
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#if defined(CONFIG_VIDEO)
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#include <video_fb.h>
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#include <mb862xx.h>
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extern GraphicDevice mb862xx;
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static const gdc_regs init_regs [] = {
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{ 0x0100, 0x00000f00 },
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{ 0x0020, 0x801401df },
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{ 0x0024, 0x00000000 },
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{ 0x0028, 0x00000000 },
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{ 0x002c, 0x00000000 },
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{ 0x0110, 0x00000000 },
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{ 0x0114, 0x00000000 },
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{ 0x0118, 0x01df0280 },
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{ 0x0004, 0x031f0000 },
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{ 0x0008, 0x027f027f },
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{ 0x000c, 0x015f028f },
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{ 0x0010, 0x020c0000 },
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{ 0x0014, 0x01df01ea },
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{ 0x0018, 0x00000000 },
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{ 0x001c, 0x01e00280 },
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{ 0x0100, 0x80010f00 },
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{ 0x0, 0x0 }
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};
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const gdc_regs *board_get_regs(void)
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{
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return init_regs;
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}
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/* Returns Lime base address */
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unsigned int board_video_init(void)
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{
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/*
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* Reset Lime controller
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*/
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gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
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udelay(500);
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gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
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mb862xx.winSizeX = 640;
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mb862xx.winSizeY = 480;
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mb862xx.gdfBytesPP = 2;
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mb862xx.gdfIndex = GDF_15BIT_555RGB;
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return CONFIG_SYS_LIME_BASE_0;
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}
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#define DEFAULT_BRIGHTNESS 0x64
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static void board_backlight_brightness(int brightness)
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{
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if (brightness > 0) {
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/* pwm duty, lamp on */
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out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
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out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
|
|
} else {
|
|
/* lamp off */
|
|
out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
|
|
out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
|
|
}
|
|
}
|
|
|
|
void board_backlight_switch(int flag)
|
|
{
|
|
char * param;
|
|
int rc;
|
|
|
|
if (flag) {
|
|
param = getenv("brightness");
|
|
rc = param ? simple_strtol(param, NULL, 10) : -1;
|
|
if (rc < 0)
|
|
rc = DEFAULT_BRIGHTNESS;
|
|
} else {
|
|
rc = 0;
|
|
}
|
|
board_backlight_brightness(rc);
|
|
}
|
|
|
|
#if defined(CONFIG_CONSOLE_EXTRA_INFO)
|
|
/*
|
|
* Return text to be printed besides the logo.
|
|
*/
|
|
void video_get_info_str(int line_number, char *info)
|
|
{
|
|
if (line_number == 1)
|
|
strcpy(info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
|
|
else
|
|
info [0] = '\0';
|
|
}
|
|
#endif /* CONFIG_CONSOLE_EXTRA_INFO */
|
|
#endif /* CONFIG_VIDEO */
|
|
|
|
void board_reset(void)
|
|
{
|
|
gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
|
|
}
|
|
|
|
#ifdef CONFIG_SPL_OS_BOOT
|
|
/*
|
|
* lwmon5 specific implementation of spl_start_uboot()
|
|
*
|
|
* RETURN
|
|
* 0 if booting into OS is selected (default)
|
|
* 1 if booting into U-Boot is selected
|
|
*/
|
|
int spl_start_uboot(void)
|
|
{
|
|
char s[8];
|
|
|
|
env_init();
|
|
getenv_f("boot_os", s, sizeof(s));
|
|
if ((s != NULL) && (strcmp(s, "yes") == 0))
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* This function is called from the SPL U-Boot version for
|
|
* early init stuff, that needs to be done for OS (e.g. Linux)
|
|
* booting. Doing it later in the real U-Boot would not work
|
|
* in case that the SPL U-Boot boots Linux directly.
|
|
*/
|
|
void spl_board_init(void)
|
|
{
|
|
const gdc_regs *regs = board_get_regs();
|
|
|
|
/*
|
|
* Setup PFC registers, mainly for ethernet support
|
|
* later on in Linux
|
|
*/
|
|
board_early_init_f();
|
|
|
|
/* enable the LSB transmitter */
|
|
gpio_write_bit(CONFIG_SYS_GPIO_LSB_ENABLE, 1);
|
|
|
|
/*
|
|
* Clear resets
|
|
*/
|
|
mtsdr(SDR0_SRST1, 0x00000000);
|
|
mtsdr(SDR0_SRST0, 0x00000000);
|
|
|
|
/*
|
|
* Reset Lime controller
|
|
*/
|
|
gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
|
|
udelay(500);
|
|
gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
|
|
|
|
out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_MB862xx_CCF);
|
|
udelay(300);
|
|
out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_MB862xx_MMR);
|
|
|
|
while (regs->index) {
|
|
out_be32((void *)(CONFIG_SYS_LIME_BASE_0 + GC_DISP_BASE) +
|
|
regs->index, regs->value);
|
|
regs++;
|
|
}
|
|
|
|
board_backlight_brightness(DEFAULT_BRIGHTNESS);
|
|
}
|
|
#endif
|
|
|