upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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547 lines
13 KiB
547 lines
13 KiB
/*
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* Copyright 2004, 2007 Freescale Semiconductor.
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*
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* (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/immap_fsl_pci.h>
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#include <spd.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include "../common/cadmus.h"
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#include "../common/eeprom.h"
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#include "../common/via.h"
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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extern long int spd_sdram(void);
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void local_bus_init(void);
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void sdram_init(void);
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int board_early_init_f (void)
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{
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return 0;
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}
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int checkboard (void)
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{
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
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volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
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/* PCI slot in USER bits CSR[6:7] by convention. */
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uint pci_slot = get_pci_slot ();
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uint cpu_board_rev = get_cpu_board_revision ();
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printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
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get_board_version (), pci_slot);
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printf ("CPU Board Revision %d.%d (0x%04x)\n",
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MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
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MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
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/*
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* Initialize local bus.
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*/
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local_bus_init ();
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/*
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* Fix CPU2 errata: A core hang possible while executing a
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* msync instruction and a snoopable transaction from an I/O
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* master tagged to make quick forward progress is present.
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*/
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ecm->eebpcr |= (1 << 16);
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/*
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* Hack TSEC 3 and 4 IO voltages.
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*/
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gur->tsec34ioovcr = 0xe7e0; /* 1110 0111 1110 0xxx */
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ecm->eedr = 0xffffffff; /* clear ecm errors */
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ecm->eeer = 0xffffffff; /* enable ecm errors */
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return 0;
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}
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long int
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initdram(int board_type)
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{
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long dram_size = 0;
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puts("Initializing\n");
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#if defined(CONFIG_DDR_DLL)
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{
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/*
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* Work around to stabilize DDR DLL MSYNC_IN.
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* Errata DDR9 seems to have been fixed.
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* This is now the workaround for Errata DDR11:
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* Override DLL = 1, Course Adj = 1, Tap Select = 0
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*/
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
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gur->ddrdllcr = 0x81000000;
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asm("sync;isync;msync");
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udelay(200);
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}
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#endif
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dram_size = spd_sdram();
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc(dram_size);
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#endif
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/*
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* SDRAM Initialization
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*/
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sdram_init();
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puts(" DDR: ");
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return dram_size;
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}
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/*
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* Initialize Local Bus
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*/
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void
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local_bus_init(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
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volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
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uint clkdiv;
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uint lbc_hz;
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sys_info_t sysinfo;
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get_sys_info(&sysinfo);
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clkdiv = (lbc->lcrr & 0x0f) * 2;
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lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
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gur->lbiuiplldcr1 = 0x00078080;
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if (clkdiv == 16) {
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gur->lbiuiplldcr0 = 0x7c0f1bf0;
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} else if (clkdiv == 8) {
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gur->lbiuiplldcr0 = 0x6c0f1bf0;
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} else if (clkdiv == 4) {
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gur->lbiuiplldcr0 = 0x5c0f1bf0;
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}
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lbc->lcrr |= 0x00030000;
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asm("sync;isync;msync");
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lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
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lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
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}
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/*
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* Initialize SDRAM memory on the Local Bus.
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*/
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void
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sdram_init(void)
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{
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#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
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uint idx;
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volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
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uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
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uint cpu_board_rev;
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uint lsdmr_common;
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puts(" SDRAM: ");
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print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
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/*
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* Setup SDRAM Base and Option Registers
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*/
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lbc->or2 = CFG_OR2_PRELIM;
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asm("msync");
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lbc->br2 = CFG_BR2_PRELIM;
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asm("msync");
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lbc->lbcr = CFG_LBC_LBCR;
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asm("msync");
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lbc->lsrt = CFG_LBC_LSRT;
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lbc->mrtpr = CFG_LBC_MRTPR;
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asm("msync");
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/*
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* MPC8548 uses "new" 15-16 style addressing.
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*/
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cpu_board_rev = get_cpu_board_revision();
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lsdmr_common = CFG_LBC_LSDMR_COMMON;
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lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
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/*
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* Issue PRECHARGE ALL command.
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*/
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lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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/*
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* Issue 8 AUTO REFRESH commands.
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*/
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for (idx = 0; idx < 8; idx++) {
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lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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}
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/*
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* Issue 8 MODE-set command.
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*/
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lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(100);
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/*
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* Issue NORMAL OP command.
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*/
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lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
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asm("sync;msync");
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*sdram_addr = 0xff;
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ppcDcbf((unsigned long) sdram_addr);
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udelay(200); /* Overkill. Must wait > 200 bus cycles */
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#endif /* enable SDRAM init */
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}
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#if defined(CFG_DRAM_TEST)
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int
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testdram(void)
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{
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uint *pstart = (uint *) CFG_MEMTEST_START;
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uint *pend = (uint *) CFG_MEMTEST_END;
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uint *p;
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printf("Testing DRAM from 0x%08x to 0x%08x\n",
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CFG_MEMTEST_START,
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CFG_MEMTEST_END);
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printf("DRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf ("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf ("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test passed.\n");
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return 0;
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}
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#endif
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#if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
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/* For some reason the Tundra PCI bridge shows up on itself as a
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* different device. Work around that by refusing to configure it.
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*/
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void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }
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static struct pci_config_table pci_mpc85xxcds_config_table[] = {
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{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},
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{0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}},
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{0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1,
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mpc85xx_config_via_usbide, {0,0,0}},
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{0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2,
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mpc85xx_config_via_usb, {0,0,0}},
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{0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3,
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mpc85xx_config_via_usb2, {0,0,0}},
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{0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5,
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mpc85xx_config_via_power, {0,0,0}},
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{0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6,
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mpc85xx_config_via_ac97, {0,0,0}},
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{},
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};
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static struct pci_controller pci1_hose = {
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config_table: pci_mpc85xxcds_config_table};
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#endif /* CONFIG_PCI */
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#ifdef CONFIG_PCI2
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static struct pci_controller pci2_hose;
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#endif /* CONFIG_PCI2 */
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#ifdef CONFIG_PCIE1
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static struct pci_controller pcie1_hose;
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#endif /* CONFIG_PCIE1 */
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int first_free_busno=0;
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void
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pci_init_board(void)
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{
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volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
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uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
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uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
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#ifdef CONFIG_PCI1
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pci1_hose;
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struct pci_config_table *table;
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uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */
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uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
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uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
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uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || (host_agent == 6);
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uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
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if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) {
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printf (" PCI: %d bit, %s MHz, %s, %s, %s\n",
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(pci_32) ? 32 : 64,
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(pci_speed == 33333000) ? "33" :
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(pci_speed == 66666000) ? "66" : "unknown",
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pci_clk_sel ? "sync" : "async",
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pci_agent ? "agent" : "host",
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pci_arb ? "arbiter" : "external-arbiter"
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);
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/* inbound */
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEMORY_BUS,
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CFG_PCI_MEMORY_PHYS,
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CFG_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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CFG_PCI1_MEM_BASE,
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CFG_PCI1_MEM_PHYS,
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CFG_PCI1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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CFG_PCI1_IO_BASE,
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CFG_PCI1_IO_PHYS,
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CFG_PCI1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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/* relocate config table pointers */
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hose->config_table = \
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(struct pci_config_table *)((uint)hose->config_table + gd->reloc_off);
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for (table = hose->config_table; table && table->vendor; table++)
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table->config_device += gd->reloc_off;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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first_free_busno=hose->last_busno+1;
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printf ("PCI on bus %02x - %02x\n",hose->first_busno,hose->last_busno);
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#ifdef CONFIG_PCIX_CHECK
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if (!(gur->pordevsr & PORDEVSR_PCI)) {
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/* PCI-X init */
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if (CONFIG_SYS_CLK_FREQ < 66000000)
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printf("PCI-X will only work at 66 MHz\n");
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reg16 = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
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| PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
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pci_hose_write_config_word(hose, bus, PCIX_COMMAND, reg16);
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}
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#endif
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} else {
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printf (" PCI: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
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#endif
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#ifdef CONFIG_PCI2
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{
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uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */
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uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
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if (pci_dual) {
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printf (" PCI2: 32 bit, 66 MHz, %s\n",
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pci2_clk_sel ? "sync" : "async");
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} else {
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printf (" PCI2: disabled\n");
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}
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}
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#else
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gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */
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#endif /* CONFIG_PCI2 */
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#ifdef CONFIG_PCIE1
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{
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volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
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extern void fsl_pci_init(struct pci_controller *hose);
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struct pci_controller *hose = &pcie1_hose;
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int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
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int pcie_configured = io_sel >= 1;
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if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
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printf ("\n PCIE connected to slot as %s (base address %x)",
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pcie_ep ? "End Point" : "Root Complex",
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(uint)pci);
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if (pci->pme_msg_det) {
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pci->pme_msg_det = 0xffffffff;
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debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
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}
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printf ("\n");
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/* inbound */
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pci_set_region(hose->regions + 0,
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CFG_PCI_MEMORY_BUS,
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CFG_PCI_MEMORY_PHYS,
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CFG_PCI_MEMORY_SIZE,
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PCI_REGION_MEM | PCI_REGION_MEMORY);
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/* outbound memory */
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pci_set_region(hose->regions + 1,
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CFG_PCIE1_MEM_BASE,
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CFG_PCIE1_MEM_PHYS,
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CFG_PCIE1_MEM_SIZE,
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PCI_REGION_MEM);
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/* outbound io */
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pci_set_region(hose->regions + 2,
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CFG_PCIE1_IO_BASE,
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CFG_PCIE1_IO_PHYS,
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CFG_PCIE1_IO_SIZE,
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PCI_REGION_IO);
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hose->region_count = 3;
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hose->first_busno=first_free_busno;
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pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
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fsl_pci_init(hose);
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printf ("PCIE on bus %d - %d\n",hose->first_busno,hose->last_busno);
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first_free_busno=hose->last_busno+1;
|
|
|
|
} else {
|
|
printf (" PCIE: disabled\n");
|
|
}
|
|
}
|
|
#else
|
|
gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
|
|
#endif
|
|
|
|
}
|
|
|
|
int last_stage_init(void)
|
|
{
|
|
unsigned short temp;
|
|
|
|
/* Change the resistors for the PHY */
|
|
/* This is needed to get the RGMII working for the 1.3+
|
|
* CDS cards */
|
|
if (get_board_version() == 0x13) {
|
|
miiphy_write(CONFIG_TSEC1_NAME,
|
|
TSEC1_PHY_ADDR, 29, 18);
|
|
|
|
miiphy_read(CONFIG_TSEC1_NAME,
|
|
TSEC1_PHY_ADDR, 30, &temp);
|
|
|
|
temp = (temp & 0xf03f);
|
|
temp |= 2 << 9; /* 36 ohm */
|
|
temp |= 2 << 6; /* 39 ohm */
|
|
|
|
miiphy_write(CONFIG_TSEC1_NAME,
|
|
TSEC1_PHY_ADDR, 30, temp);
|
|
|
|
miiphy_write(CONFIG_TSEC1_NAME,
|
|
TSEC1_PHY_ADDR, 29, 3);
|
|
|
|
miiphy_write(CONFIG_TSEC1_NAME,
|
|
TSEC1_PHY_ADDR, 30, 0x8000);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
|
void
|
|
ft_pci_setup(void *blob, bd_t *bd)
|
|
{
|
|
int node, tmp[2];
|
|
const char *path;
|
|
|
|
node = fdt_path_offset(blob, "/aliases");
|
|
tmp[0] = 0;
|
|
if (node >= 0) {
|
|
#ifdef CONFIG_PCI1
|
|
path = fdt_getprop(blob, node, "pci0", NULL);
|
|
if (path) {
|
|
tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
|
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
|
}
|
|
#endif
|
|
#ifdef CONFIG_PCIE1
|
|
path = fdt_getprop(blob, node, "pci1", NULL);
|
|
if (path) {
|
|
tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
|
|
do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
#endif
|
|
|