upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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179 lines
4.9 KiB
179 lines
4.9 KiB
/*
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* Copyright 2004 Freescale Semiconductor.
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* Jeff Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <config.h>
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#include <mpc86xx.h>
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/*
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* LAW(Local Access Window) configuration:
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
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* 0xc000_0000 0xdfff_ffff RapidIO 512M
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* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
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* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
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* 0xf800_0000 0xf80f_ffff CCSRBAR 1M
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* 0xf810_0000 0xf81f_ffff PIXIS 1M
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* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
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*
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* Notes:
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* CCSRBAR don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*/
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#if !defined(CONFIG_SPD_EEPROM)
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#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#else
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#define LAWBAR1 0
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#define LAWAR1 ((LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
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#endif
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#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff)
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
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/*
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* This is not so much the SDRAM map as it is the whole localbus map.
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*/
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#define LAWBAR4 ((0xf8100000>>12) & 0xffffff)
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
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#define LAWBAR5 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff)
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#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
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#define LAWBAR6 ((CFG_PCI2_IO_PHYS>>12) & 0xffffff)
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#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
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#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
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#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
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#if !defined(CONFIG_SPD_EEPROM)
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#define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
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#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#else
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#define LAWBAR8 0
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#define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
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#endif
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#define LAWBAR9 ((CFG_RIO_MEM_PHYS>>12) & 0xfffff)
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#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
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.section .bootpg, "ax"
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.globl law_entry
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law_entry:
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lis r7,CFG_CCSRBAR@h
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ori r7,r7,CFG_CCSRBAR@l
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addi r4,r7,0
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addi r5,r7,0
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/* Skip LAWAR0, start at LAWAR1 */
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lis r6,LAWBAR1@h
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ori r6,r6,LAWBAR1@l
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stwu r6, 0xc28(r4)
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lis r6,LAWAR1@h
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ori r6,r6,LAWAR1@l
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stwu r6, 0xc30(r5)
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/* LAWBAR2, LAWAR2 */
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lis r6,LAWBAR2@h
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ori r6,r6,LAWBAR2@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR2@h
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ori r6,r6,LAWAR2@l
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stwu r6, 0x20(r5)
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/* LAWBAR3, LAWAR3 */
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lis r6,LAWBAR3@h
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ori r6,r6,LAWBAR3@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR3@h
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ori r6,r6,LAWAR3@l
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stwu r6, 0x20(r5)
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/* LAWBAR4, LAWAR4 */
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lis r6,LAWBAR4@h
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ori r6,r6,LAWBAR4@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR4@h
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ori r6,r6,LAWAR4@l
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stwu r6, 0x20(r5)
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/* LAWBAR5, LAWAR5 */
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lis r6,LAWBAR5@h
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ori r6,r6,LAWBAR5@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR5@h
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ori r6,r6,LAWAR5@l
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stwu r6, 0x20(r5)
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/* LAWBAR6, LAWAR6 */
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lis r6,LAWBAR6@h
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ori r6,r6,LAWBAR6@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR6@h
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ori r6,r6,LAWAR6@l
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stwu r6, 0x20(r5)
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/* LAWBAR7, LAWAR7 */
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lis r6,LAWBAR7@h
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ori r6,r6,LAWBAR7@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR7@h
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ori r6,r6,LAWAR7@l
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stwu r6, 0x20(r5)
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/* LAWBAR8, LAWAR8 */
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lis r6,LAWBAR8@h
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ori r6,r6,LAWBAR8@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR8@h
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ori r6,r6,LAWAR8@l
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stwu r6, 0x20(r5)
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/* LAWBAR9, LAWAR9 */
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lis r6,LAWBAR9@h
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ori r6,r6,LAWBAR9@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR9@h
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ori r6,r6,LAWAR9@l
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stwu r6, 0x20(r5)
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blr
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