upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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260 lines
6.5 KiB
260 lines
6.5 KiB
/*
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* (C) Copyright 2005
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* Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <command.h>
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#include <malloc.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern void lxt971_no_sleep(void);
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/* fpga configuration data - not compressed, generated by bin2c */
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const unsigned char fpgadata[] =
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{
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#include "fpgadata.c"
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};
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int filesize = sizeof(fpgadata);
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int board_early_init_f (void)
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{
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
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mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
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mtdcr(uictr, 0x10000000); /* set int trigger levels */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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/*
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* EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
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*/
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mtebc (epcr, 0xa8400000); /* ebc always driven */
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/*
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* Reset CPLD via GPIO12 (CS3) pin
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);
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udelay(1000); /* wait 1ms */
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);
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udelay(1000); /* wait 1ms */
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int misc_init_f (void)
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{
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return 0; /* dummy implementation */
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}
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int misc_init_r (void)
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{
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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/*
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* Setup and enable EEPROM write protection
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
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/*
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* Set NAND-FLASH GPIO signals to default
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*/
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out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
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return (0);
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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char str[64];
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int flashcnt;
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int delay;
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volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000);
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volatile unsigned char *ver_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1001);
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puts ("Board: ");
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if (getenv_r("serial#", str, sizeof(str)) == -1) {
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puts ("### No HW ID - assuming CMS700");
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} else {
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puts(str);
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}
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printf(" (PLD-Version=%02d)\n", *ver_reg);
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/*
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* Flash LEDs
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*/
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for (flashcnt = 0; flashcnt < 3; flashcnt++) {
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*led_reg = 0x00; /* LEDs off */
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for (delay = 0; delay < 100; delay++)
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udelay(1000);
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*led_reg = 0x0f; /* LEDs on */
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for (delay = 0; delay < 50; delay++)
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udelay(1000);
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}
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*led_reg = 0x70;
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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unsigned long val;
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mtdcr(memcfga, mem_mb0cf);
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val = mfdcr(memcfgd);
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#if 0
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printf("\nmb0cf=%x\n", val); /* test-only */
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printf("strap=%x\n", mfdcr(strap)); /* test-only */
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#endif
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return (4*1024*1024 << ((val & 0x000e0000) >> 17));
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}
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/* ------------------------------------------------------------------------- */
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#if defined(CFG_EEPROM_WREN)
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/* Input: <dev_addr> I2C address of EEPROM device to enable.
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* <state> -1: deliver current state
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* 0: disable write
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* 1: enable write
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* Returns: -1: wrong device address
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* 0: dis-/en- able done
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* 0/1: current state if <state> was -1.
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*/
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int eeprom_write_enable (unsigned dev_addr, int state)
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{
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if (CFG_I2C_EEPROM_ADDR != dev_addr) {
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return -1;
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} else {
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switch (state) {
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case 1:
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/* Enable write access, clear bit GPIO_SINT2. */
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out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
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state = 0;
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break;
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case 0:
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/* Disable write access, set bit GPIO_SINT2. */
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out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
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state = 0;
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break;
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default:
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/* Read current status back. */
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state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
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break;
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}
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}
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return state;
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}
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int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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int query = argc == 1;
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int state = 0;
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if (query) {
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/* Query write access state. */
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
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if (state < 0) {
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puts ("Query of write access state failed.\n");
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} else {
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printf ("Write access for device 0x%0x is %sabled.\n",
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CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
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state = 0;
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}
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} else {
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if ('0' == argv[1][0]) {
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/* Disable write access. */
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
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} else {
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/* Enable write access. */
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state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
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}
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if (state < 0) {
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puts ("Setup of write access state failed.\n");
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}
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}
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return state;
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}
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U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
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"eepwren - Enable / disable / query EEPROM write access\n",
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NULL);
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#endif /* #if defined(CFG_EEPROM_WREN) */
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/* ------------------------------------------------------------------------- */
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#if (CONFIG_COMMANDS & CFG_CMD_NAND)
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#include <linux/mtd/nand_legacy.h>
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extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
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void nand_init(void)
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{
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nand_probe(CFG_NAND_BASE);
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if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
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print_size(nand_dev_desc[0].totlen, "\n");
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}
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}
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#endif
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void reset_phy(void)
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{
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#ifdef CONFIG_LXT971_NO_SLEEP
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/*
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* Disable sleep mode in LXT971
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*/
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lxt971_no_sleep();
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#endif
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}
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