upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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242 lines
7.9 KiB
242 lines
7.9 KiB
/*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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* David Updegraff, Cray, Inc. dave@cray.com: our 405 is walnut-lite..
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* board/config.h - configuration options, board specific
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_CRAYL1
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/*
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* High Level Configuration Options
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* (easy to change)
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*/
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#define CONFIG_405GP 1 /* This is a PPC405 CPU */
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#define CONFIG_4xx 1 /* ...member of PPC405 family */
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#define CONFIG_SYS_CLK_FREQ 25000000
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#define CONFIG_BAUDRATE 9600
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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#define CONFIG_MII 1 /* MII PHY management */
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#define CONFIG_PHY_ADDR 1 /* PHY address; handling of ENET */
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* early setup for 405gp */
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#define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */
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/* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to
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* keep possible initrd ramdisk decompression out. This is in k (1024 bytes)
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#define CONFIG_PRAM 16
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*/
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#define CONFIG_LOADADDR 0x100000 /* where TFTP images go */
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#undef CONFIG_BOOTARGS
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/* Bootcmd is overridden by the bootscript in board/cray/L1
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*/
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#define CFG_AUTOLOAD "no"
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#define CONFIG_BOOTCOMMAND "dhcp"
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/*
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* ..during experiments..
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#define CONFIG_SERVERIP 10.0.0.1
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#define CONFIG_ETHADDR 00:40:a6:80:14:5
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*/
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#define CONFIG_HARD_I2C 1 /* hardware support for i2c */
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#define CONFIG_SDRAM_BANK0 1
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_SLAVE 0x7F
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#define CFG_I2C_EEPROM_ADDR 0x57
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_IDENT_STRING "Cray L1"
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#define CONFIG_ENV_OVERWRITE 1
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#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
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#define CFG_HUSH_PARSER 1
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#define CFG_PROMPT_HUSH_PS2 "> "
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#define CONFIG_AUTOSCRIPT 1
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/*
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* Command line configuration.
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*/
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#define CONFIG_CMD_BDI
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#define CONFIG_CMD_IMI
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#define CONFIG_CMD_FLASH
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#define CONFIG_CMD_MEMORY
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#define CONFIG_CMD_NET
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_CONSOLE
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#define CONFIG_CMD_ASKENV
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#define CONFIG_CMD_ECHO
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#define CONFIG_CMD_IMMAP
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#define CONFIG_CMD_REGINFO
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_DATE
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#define CONFIG_CMD_RUN
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#define CONFIG_CMD_I2C
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#define CONFIG_CMD_EEPROM
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#define CONFIG_CMD_DIAG
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#define CONFIG_CMD_AUTOSCRIPT
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#define CONFIG_CMD_SETGETDCR
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_SUBNETMASK
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#define CONFIG_BOOTP_GATEWAY
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#define CONFIG_BOOTP_HOSTNAME
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#define CONFIG_BOOTP_BOOTPATH
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#define CONFIG_BOOTP_VENDOREX
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#define CONFIG_BOOTP_DNS
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* how many time to fail & restart a net-TFTP before giving up & resetting
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* the board hoping that a reset of net interface might help..
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*/
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#define CONFIG_NET_RESET 5
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/*
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* bauds. Just to make it compile; in our case, I read the base_baud
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* from the DCR anyway, so its kinda-tied to the above ref. clock which in turn
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* drives the system clock.
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*/
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#define CFG_BASE_BAUD 403225
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#define CFG_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
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/*
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* Miscellaneous configurable options
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*/
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#define CFG_PROMPT "=> " /* Monitor Command Prompt */
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#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
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#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
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#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
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#define CFG_MAXARGS 16 /* max number of command args */
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#define CFG_LOAD_ADDR 0x100000 /* where to load what we get from TFTP */
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#define CFG_TFTP_LOADADDR CFG_LOAD_ADDR
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#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
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#define CFG_DRAM_TEST 1
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/*-----------------------------------------------------------------------
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* Start addresses for the final memory configuration
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* (Set up by the startup code)
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* Please note that CFG_SDRAM_BASE _must_ start at 0
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*/
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#define CFG_SDRAM_BASE 0x00000000
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#define CFG_FLASH_BASE 0xFFC00000
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#define CFG_MONITOR_BASE TEXT_BASE
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#define CFG_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 8 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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/*-----------------------------------------------------------------------
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* FLASH organization
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*/
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#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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/* BEG ENVIRONNEMENT FLASH: needs to be a whole FlashSector */
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#define CFG_ENV_OFFSET 0x3c8000
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment area */
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#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
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/* Memory tests: U-BOOT relocates itself to the top of Ram, so its at
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* 32meg-(128k+some_malloc_space+copy-of-ENV sector)..
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*/
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#define CFG_SDRAM_SIZE 32 /* megs of ram */
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#define CFG_MEMTEST_START 0x2000 /* memtest works from the end of */
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/* the exception vector table */
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/* to the end of the DRAM */
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/* less monitor and malloc area */
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#define CFG_STACK_USAGE 0x10000 /* Reserve 64k for the stack usage */
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#define CFG_MALLOC_LEN (128 << 10) /* 128k for malloc space */
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#define CFG_MEM_END_USAGE ( CFG_MONITOR_LEN \
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+ CFG_MALLOC_LEN \
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+ CFG_ENV_SECT_SIZE \
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+ CFG_STACK_USAGE )
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#define CFG_MEMTEST_END (CFG_SDRAM_SIZE * 1024 * 1024 - CFG_MEM_END_USAGE)
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/* END ENVIRONNEMENT FLASH */
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/*
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* Init Memory Controller:
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*
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* BR0/1 and OR0/1 (FLASH)
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*/
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#define FLASH_BASE0_PRELIM CFG_FLASH_BASE /* FLASH bank #0 */
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/*-----------------------------------------------------------------------
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* Definitions for initial stack pointer and data area (in OnChipMem )
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*/
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#if 1
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/* On Chip Memory location */
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#define CFG_TEMP_STACK_OCM 1
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#define CFG_OCM_DATA_ADDR 0xF0000000
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#define CFG_OCM_DATA_SIZE 0x1000
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#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
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#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
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#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#else
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#define CFG_OCM_DATA_ADDR 0xF0000000
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#define CFG_OCM_DATA_SIZE 0x1000
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#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
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#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
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#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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#endif
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/*-----------------------------------------------------------------------
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* Definitions for Serial Presence Detect EEPROM address
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*/
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#define EEPROM_WRITE_ADDRESS 0xA0
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#define EEPROM_READ_ADDRESS 0xA1
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/*
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* Internal Definitions
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*
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* Boot Flags
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*/
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#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
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#define BOOTFLAG_WARM 0x02 /* Software reboot */
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#endif /* __CONFIG_H */
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