upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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194 lines
7.0 KiB
194 lines
7.0 KiB
/*
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* (C) Copyright 2005
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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* John Otken, jotken@softadvances.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/************************************************************************
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* luan.h - configuration for LUAN board
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***********************************************************************/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*-----------------------------------------------------------------------
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* High Level Configuration Options
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*----------------------------------------------------------------------*/
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#define CONFIG_LUAN 1 /* Board is Luan */
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#define CONFIG_440SP 1 /* Specific PPC440SP support */
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#define CONFIG_4xx 1 /* PPC4xx family */
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#define CONFIG_440 1
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#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
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/*
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* Include common defines/options for all AMCC eval boards
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*/
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#define CONFIG_HOSTNAME luan
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#include "amcc-common.h"
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#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
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#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
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/*-----------------------------------------------------------------------
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* Base addresses -- Note these are effective addresses where the
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* actual resources get mapped (not physical addresses)
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*----------------------------------------------------------------------*/
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#define CFG_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */
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#define CFG_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */
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#define CFG_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */
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#define CFG_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */
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#define CFG_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */
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#define CFG_PERIPHERAL_BASE 0xf0000000 /* internal peripherals */
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#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
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#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
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#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
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#if CFG_LARGE_FLASH == 0xffc00000
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#define CFG_FLASH_BASE CFG_LARGE_FLASH
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#else
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#define CFG_FLASH_BASE CFG_SMALL_FLASH
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#endif
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#if CFG_SRAM_BASE
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#define CFG_KBYTES_SDRAM 1024*2
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#else
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#define CFG_KBYTES_SDRAM 1024
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#endif
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/*-----------------------------------------------------------------------
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* Initial RAM & stack pointer (placed in SDRAM)
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*----------------------------------------------------------------------*/
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#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE
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#define CFG_INIT_RAM_END (8 << 10)
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#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
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#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
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#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
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/*-----------------------------------------------------------------------
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* Serial Port
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*----------------------------------------------------------------------*/
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#define CFG_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */
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#undef CONFIG_UART1_CONSOLE /* define if you want console on UART1 */
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/*-----------------------------------------------------------------------
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* Environment
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*----------------------------------------------------------------------*/
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/*
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* Define here the location of the environment variables (FLASH or EEPROM).
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* Note: DENX encourages to use redundant environment in FLASH.
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*/
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#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
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/*-----------------------------------------------------------------------
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* FLASH related
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*----------------------------------------------------------------------*/
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#define CFG_MAX_FLASH_BANKS 3 /* max number of memory banks */
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#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
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#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
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#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
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#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CFG_FLASH_ADDR0 0x555
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#define CFG_FLASH_ADDR1 0x2aa
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#define CFG_FLASH_WORD_SIZE unsigned char
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#ifdef CFG_ENV_IS_IN_FLASH
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#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
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#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
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/* Address and size of Redundant Environment Sector */
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#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
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#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
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#endif /* CFG_ENV_IS_IN_FLASH */
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/*-----------------------------------------------------------------------
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* DDR SDRAM
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*----------------------------------------------------------------------*/
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#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
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#define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
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#define CONFIG_DDR_ECC 1 /* with ECC support */
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/*-----------------------------------------------------------------------
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* I2C
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*----------------------------------------------------------------------*/
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#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
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#define CFG_I2C_MULTI_EEPROMS
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#define CFG_I2C_EEPROM_ADDR (0xa8>>1)
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#define CFG_I2C_EEPROM_ADDR_LEN 1
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#define CFG_EEPROM_PAGE_WRITE_ENABLE
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#define CFG_EEPROM_PAGE_WRITE_BITS 3
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#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
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/*
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* Default environment variables
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*/
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#define CONFIG_EXTRA_ENV_SETTINGS \
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CONFIG_AMCC_DEF_ENV \
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CONFIG_AMCC_DEF_ENV_PPC \
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CONFIG_AMCC_DEF_ENV_NOR_UPD \
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"kernel_addr=fc000000\0" \
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"ramdisk_addr=fc100000\0" \
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""
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#define CONFIG_HAS_ETH0
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#define CONFIG_PHY_ADDR 1
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#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
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#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
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#ifdef DEBUG
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#define CONFIG_PANIC_HANG
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#else
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#define CONFIG_HW_WATCHDOG /* watchdog */
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#endif
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/*
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* Commands additional to the ones defined in amcc-common.h
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*/
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#define CONFIG_CMD_PCI
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#define CONFIG_CMD_SDRAM
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/*-----------------------------------------------------------------------
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* PCI stuff
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*-----------------------------------------------------------------------
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*/
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#if defined(CONFIG_CMD_PCI)
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/* General PCI */
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#define CONFIG_PCI /* include pci support */
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#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
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#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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/* Board-specific PCI */
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#define CFG_PCI_TARGET_INIT
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#undef CFG_PCI_MASTER_INIT
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#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
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#define CFG_PCI_SUBSYS_DEVICEID 0x4403 /* whatever */
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#endif
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#endif /* __CONFIG_H */
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