upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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90 lines
1.8 KiB
90 lines
1.8 KiB
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd.
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*/
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/dts-v1/;
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#include "rk322x.dtsi"
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/ {
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model = "Rockchip RK3229 Evaluation board";
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compatible = "rockchip,rk3229-evb", "rockchip,rk3229";
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chosen {
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stdout-path = &uart2;
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};
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memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 0x40000000>;
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};
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ext_gmac: ext_gmac {
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compatible = "fixed-clock";
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clock-frequency = <125000000>;
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clock-output-names = "ext_gmac";
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#clock-cells = <0>;
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};
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vcc_phy: vcc-phy-regulator {
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compatible = "regulator-fixed";
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enable-active-high;
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regulator-name = "vcc_phy";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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&dmc {
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rockchip,pctl-timing = <0x96 0xC8 0x1F3 0xF 0x8000004D 0x4 0x4E 0x6 0x3
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0x0 0x6 0x5 0xC 0x10 0x6 0x4 0x4
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0x5 0x4 0x200 0x3 0xA 0x40 0x0 0x1
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0x5 0x5 0x3 0xC 0x1E 0x100 0x0 0x4
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0x0 0x924>;
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rockchip,phy-timing = <0x220 0x1 0x0 0x0 0x0 0x4 0x60>;
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rockchip,sdram-params = <0x428B188 0x0 0x21 0x472 0x15
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0 300 3 0 120>;
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};
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&gmac {
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assigned-clocks = <&cru SCLK_MAC_EXTCLK>, <&cru SCLK_MAC>;
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assigned-clock-parents = <&ext_gmac>, <&cru SCLK_MAC_EXTCLK>;
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clock_in_out = "input";
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phy-supply = <&vcc_phy>;
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phy-mode = "rgmii";
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pinctrl-names = "default";
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pinctrl-0 = <&rgmii_pins>;
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snps,reset-gpio = <&gpio2 RK_PD0 GPIO_ACTIVE_LOW>;
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snps,reset-active-low;
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snps,reset-delays-us = <0 10000 1000000>;
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tx_delay = <0x30>;
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rx_delay = <0x10>;
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status = "okay";
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};
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&emmc {
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u-boot,dm-pre-reloc;
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status = "okay";
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};
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&sdmmc {
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status = "okay";
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bus-width = <4>;
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cap-mmc-highspeed;
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cap-sd-highspeed;
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card-detect-delay = <200>;
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disable-wp;
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num-slots = <1>;
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supports-sd;
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};
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&uart2 {
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status = "okay";
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};
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&usb20_otg {
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status = "okay";
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};
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