upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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62 lines
1.3 KiB
62 lines
1.3 KiB
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013 Imagination Technologies
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* Author: Paul Burton <paul.burton@mips.com>
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*
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* Setup code for the FDC37M817 super I/O controller
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*/
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#include <common.h>
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#include <asm/io.h>
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#define SIO_CONF_PORT 0x3f0
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#define SIO_DATA_PORT 0x3f1
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enum sio_conf_key {
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SIOCONF_DEVNUM = 0x07,
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SIOCONF_ACTIVATE = 0x30,
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SIOCONF_ENTER_SETUP = 0x55,
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SIOCONF_BASE_HIGH = 0x60,
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SIOCONF_BASE_LOW = 0x61,
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SIOCONF_PRIMARY_INT = 0x70,
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SIOCONF_EXIT_SETUP = 0xaa,
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SIOCONF_MODE = 0xf0,
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};
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static struct {
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u8 key;
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u8 data;
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} sio_config[] = {
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/* tty0 */
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{ SIOCONF_DEVNUM, 0x04 },
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{ SIOCONF_BASE_HIGH, 0x03 },
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{ SIOCONF_BASE_LOW, 0xf8 },
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{ SIOCONF_MODE, 0x02 },
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{ SIOCONF_PRIMARY_INT, 0x04 },
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{ SIOCONF_ACTIVATE, 0x01 },
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/* tty1 */
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{ SIOCONF_DEVNUM, 0x05 },
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{ SIOCONF_BASE_HIGH, 0x02 },
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{ SIOCONF_BASE_LOW, 0xf8 },
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{ SIOCONF_MODE, 0x02 },
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{ SIOCONF_PRIMARY_INT, 0x03 },
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{ SIOCONF_ACTIVATE, 0x01 },
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};
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void malta_superio_init(void)
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{
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unsigned i;
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/* enter config state */
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outb(SIOCONF_ENTER_SETUP, SIO_CONF_PORT);
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/* configure peripherals */
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for (i = 0; i < ARRAY_SIZE(sio_config); i++) {
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outb(sio_config[i].key, SIO_CONF_PORT);
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outb(sio_config[i].data, SIO_DATA_PORT);
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}
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/* exit config state */
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outb(SIOCONF_EXIT_SETUP, SIO_CONF_PORT);
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}
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