upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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145 lines
3.2 KiB
145 lines
3.2 KiB
/*
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* keystone2: commands for clocks
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/psc_defs.h>
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struct pll_init_data cmd_pll_data = {
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.pll = MAIN_PLL,
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.pll_m = 16,
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.pll_d = 1,
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.pll_od = 2,
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};
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int do_pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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if (argc != 5)
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goto pll_cmd_usage;
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if (strncmp(argv[1], "pa", 2) == 0)
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cmd_pll_data.pll = PASS_PLL;
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#ifndef CONFIG_SOC_K2E
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else if (strncmp(argv[1], "arm", 3) == 0)
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cmd_pll_data.pll = TETRIS_PLL;
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#endif
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#ifdef CONFIG_SOC_K2HK
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else if (strncmp(argv[1], "ddr3a", 5) == 0)
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cmd_pll_data.pll = DDR3A_PLL;
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else if (strncmp(argv[1], "ddr3b", 5) == 0)
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cmd_pll_data.pll = DDR3B_PLL;
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#else
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else if (strncmp(argv[1], "ddr3", 4) == 0)
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cmd_pll_data.pll = DDR3_PLL;
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#endif
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else
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goto pll_cmd_usage;
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cmd_pll_data.pll_m = simple_strtoul(argv[2], NULL, 10);
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cmd_pll_data.pll_d = simple_strtoul(argv[3], NULL, 10);
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cmd_pll_data.pll_od = simple_strtoul(argv[4], NULL, 10);
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printf("Trying to set pll %d; mult %d; div %d; OD %d\n",
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cmd_pll_data.pll, cmd_pll_data.pll_m,
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cmd_pll_data.pll_d, cmd_pll_data.pll_od);
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init_pll(&cmd_pll_data);
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return 0;
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pll_cmd_usage:
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return cmd_usage(cmdtp);
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}
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#ifdef CONFIG_SOC_K2HK
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U_BOOT_CMD(
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pllset, 5, 0, do_pll_cmd,
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"set pll multiplier and pre divider",
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"<pa|arm|ddr3a|ddr3b> <mult> <div> <OD>\n"
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);
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#endif
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#ifdef CONFIG_SOC_K2E
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U_BOOT_CMD(
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pllset, 5, 0, do_pll_cmd,
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"set pll multiplier and pre divider",
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"<pa|ddr3> <mult> <div> <OD>\n"
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);
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#endif
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int do_getclk_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned int clk;
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unsigned int freq;
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if (argc != 2)
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goto getclk_cmd_usage;
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clk = simple_strtoul(argv[1], NULL, 10);
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freq = clk_get_rate(clk);
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printf("clock index [%d] - frequency %u\n", clk, freq);
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return 0;
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getclk_cmd_usage:
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return cmd_usage(cmdtp);
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}
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U_BOOT_CMD(
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getclk, 2, 0, do_getclk_cmd,
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"get clock rate",
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"<clk index>\n"
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#ifdef CONFIG_SOC_K2HK
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"See the 'enum clk_e' in the clock-k2hk.h for clk indexes\n"
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#endif
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#ifdef CONFIG_SOC_K2E
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"See the 'enum clk_e' in the clock-k2e.h for clk indexes\n"
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#endif
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);
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int do_psc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int psc_module;
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int res;
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if (argc != 3)
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goto psc_cmd_usage;
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psc_module = simple_strtoul(argv[1], NULL, 10);
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if (strcmp(argv[2], "en") == 0) {
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res = psc_enable_module(psc_module);
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printf("psc_enable_module(%d) - %s\n", psc_module,
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(res) ? "ERROR" : "OK");
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return 0;
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}
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if (strcmp(argv[2], "di") == 0) {
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res = psc_disable_module(psc_module);
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printf("psc_disable_module(%d) - %s\n", psc_module,
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(res) ? "ERROR" : "OK");
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return 0;
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}
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if (strcmp(argv[2], "domain") == 0) {
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res = psc_disable_domain(psc_module);
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printf("psc_disable_domain(%d) - %s\n", psc_module,
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(res) ? "ERROR" : "OK");
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return 0;
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}
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psc_cmd_usage:
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return cmd_usage(cmdtp);
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}
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U_BOOT_CMD(
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psc, 3, 0, do_psc_cmd,
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"<enable/disable psc module os disable domain>",
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"<mod/domain index> <en|di|domain>\n"
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"See the hardware.h for Power and Sleep Controller (PSC) Domains\n"
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);
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