upstream u-boot with additional patches for our devices/boards:
https://lists.denx.de/pipermail/u-boot/2017-March/282789.html (AXP crashes) ;
Gbit ethernet patch for some LIME2 revisions ;
with SPI flash support
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101 lines
2.7 KiB
101 lines
2.7 KiB
/*
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* SPDX-License-Identifier: GPL-2.0 ibm-pibs
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*/
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/*-----------------------------------------------------------------------------+
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| File Name: miiphy.c
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| Function: This module has utilities for accessing the MII PHY through
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| the EMAC3 macro.
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| Author: Mark Wisner
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| Change Activity-
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| Date Description of Change BY
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| --------- --------------------- ---
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| 05-May-99 Created MKW
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| 01-Jul-99 Changed clock setting of sta_reg from 66MHz to 50MHz to
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| better match OPB speed. Also modified delay times. JWB
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| 29-Jul-99 Added Full duplex support MKW
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| 24-Aug-99 Removed printf from dp83843_duplex() JWB
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| 19-Jul-00 Ported to esd cpci405 sr
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| 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
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| <travis.sawyer@sandburst.com>
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+-----------------------------------------------------------------------------*/
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#include <common.h>
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#include <miiphy.h>
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#include "IxOsal.h"
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#include "IxEthAcc.h"
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#include "IxEthAcc_p.h"
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#include "IxEthAccMac_p.h"
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#include "IxEthAccMii_p.h"
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/***********************************************************/
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/* Dump out to the screen PHY regs */
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/***********************************************************/
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void miiphy_dump (char *devname, unsigned char addr)
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{
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unsigned long i;
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unsigned short data;
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for (i = 0; i < 0x1A; i++) {
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if (miiphy_read (devname, addr, i, &data)) {
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printf ("read error for reg %lx\n", i);
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return;
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}
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printf ("Phy reg %lx ==> %4x\n", i, data);
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/* jump to the next set of regs */
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if (i == 0x07)
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i = 0x0f;
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} /* end for loop */
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} /* end dump */
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/***********************************************************/
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/* (Re)start autonegotiation */
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/***********************************************************/
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int phy_setup_aneg (char *devname, unsigned char addr)
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{
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unsigned short ctl, adv;
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/* Setup standard advertise */
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miiphy_read (devname, addr, MII_ADVERTISE, &adv);
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adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 |
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LPA_100FULL | LPA_100HALF | LPA_10FULL |
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LPA_10HALF);
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miiphy_write (devname, addr, MII_ADVERTISE, adv);
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/* Start/Restart aneg */
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miiphy_read (devname, addr, MII_BMCR, &ctl);
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ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
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miiphy_write (devname, addr, MII_BMCR, ctl);
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return 0;
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}
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int npe_miiphy_read (const char *devname, unsigned char addr,
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unsigned char reg, unsigned short *value)
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{
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u16 val;
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ixEthAccMiiReadRtn(addr, reg, &val);
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*value = val;
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return 0;
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} /* phy_read */
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int npe_miiphy_write (const char *devname, unsigned char addr,
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unsigned char reg, unsigned short value)
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{
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ixEthAccMiiWriteRtn(addr, reg, value);
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return 0;
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} /* phy_write */
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